Semiconductor device

Patent metadata

Field	Value
Publication number	US-10079231-B2
Application number	US-201615291276-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Oct 15, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first wiring, and a second wiring. The first transistor includes a first gate and a second gate. The first gate and the second gate overlap with each other with a semiconductor therebetween. The first wiring and the second wiring are supplied with a high power supply potential and a low power supply potential, respectively. A first terminal of the first transistor is electrically connected to the first gate and the first wiring. A second terminal of the first transistor is electrically connected to the second gate. The second terminal of the first transistor is electrically connected to the second wiring through the second transistor and the third transistor. The first transistor, the second transistor, and the third transistor are preferably n-channel transistors.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first wiring; and
a second wiring,
wherein the first transistor comprises a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor therebetween,
wherein the first wiring is configured to transmit a high power supply potential,
wherein the second wiring is configured to transmit a low power supply potential,
wherein a first terminal of the first transistor is electrically connected to the first gate,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein a second terminal of the first transistor is electrically connected to the second gate,
wherein the second terminal of the first transistor is electrically connected to the second wiring through the second transistor and the third transistor, and
wherein the first transistor, the second transistor, and the third transistor are n-channel transistors.

2. The semiconductor device according to claim 1 ,
wherein the semiconductor includes an oxide semiconductor.

3. An electronic device comprising:
the semiconductor device according to claim 1 ; and
at least one of a microphone, a speaker, a display portion, and an operation button.

4. A semiconductor device comprising:
a first transistor;
a second transistor;
a first wiring; and
a second wiring,
wherein the first transistor comprises a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a first semiconductor therebetween,
wherein the second transistor comprises a third gate and a fourth gate,
wherein the third gate and the fourth gate overlap with each other with a second semiconductor therebetween,
wherein the first wiring is configured to transmit a first power supply potential,
wherein the second wiring is configured to transmit a second power supply potential,
wherein a first terminal of the first transistor is electrically connected to the first gate,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein a second terminal of the first transistor is electrically connected to the second gate,
wherein the second terminal of the first transistor is electrically connected to the second wiring through the second transistor,
wherein the first transistor and the second transistor have the same polarity,
wherein the first power supply potential and the second power supply potential are different from each other,
wherein the third gate is configured to receive a first data, and
wherein the second terminal of the first transistor is configured to output a second data.

5. The semiconductor device according to claim 4 ,
wherein the first power supply potential is a high power supply potential,
wherein the second power supply potential is a low power supply potential, and
wherein the first transistor and the second transistor are n-channel transistors.

6. The semiconductor device according to claim 5 ,
wherein the first data is data A,
wherein the fourth gate is configured to receive data B,
wherein the second data is data Z,
wherein the data A, the data B, and the data Z are each of a Boolean data type, and
wherein the data Z is denoted by NOT(A+B).

7. The semiconductor device according to claim 5 ,
wherein the first semiconductor and the second semiconductor each include an oxide semiconductor.

8. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first wiring; and
a second wiring,
wherein the first transistor comprises a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a first semiconductor therebetween,
wherein the second transistor comprises a third gate and a fourth gate,
wherein the third gate and the fourth gate overlap with each other with a second semiconductor therebetween,
wherein the third transistor comprises a fifth gate and a sixth gate,
wherein the fifth gate and the sixth gate overlap with each other with a third semiconductor therebetween,
wherein the first wiring is configured to transmit a high power supply potential,
wherein the second wiring is configured to transmit a low power supply potential,
wherein a first terminal of the first transistor is electrically connected to the first gate,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein a second terminal of the first transistor is electrically connected to the second gate,
wherein the second terminal of the first transistor is electrically connected to the second wiring through the second transistor and the third transistor, and
wherein the first transistor, the second transistor, and the third transistor are n-channel transistors.

9. The semiconductor device according to claim 8 ,
wherein the third gate is configured to receive data A,
wherein the fourth gate is configured to receive data C,
wherein the fifth gate is configured to receive data B,
wherein the sixth gate is configured to receive the data C,
wherein the second terminal of the first transistor is configured to output data Z,
wherein the data A, the data B, the data C, and the data Z are each of a Boolean data type, and
wherein the data Z is denoted by NOT((A×B)+C).

10. The semiconductor device according to claim 8 ,
wherein the first semiconductor, the second semiconductor, and the third semiconductor each include an oxide semiconductor.

11. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first wiring; and
a second wiring,
wherein the first transistor comprises a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a first semiconductor therebetween,
wherein the second transistor comprises a third gate and a fourth gate,
wherein the third gate and the fourth gate overlap with each other with a second semiconductor therebetween,
wherein the first wiring is configured to transmit a high power supply potential,
wherein the second wiring is configured to transmit a low power supply potential,
wherein a first terminal of the first transistor is electrically connected to the first gate,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein a second terminal of the first transistor is electrically connected to the second gate,
wherein the second terminal of the first transistor is electrically connected to the second wiring through the second transistor and the third transistor, and
wherein the first transistor, the second transistor, and the third transistor are n-channel transistors.

12. The semiconductor device according to claim 11 ,
wherein the first semiconductor and the second semiconductor each include an oxide semiconductor.

13. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first wiring; and
a second wiring,
wherein the first transistor comprises a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor therebetween,
wherein the first wiring is configured to transmit a first power supply potential,
wherein the second wiring is configured to transmit a second power supply potential,
wherein a first terminal of the first transistor is electrically connected to the first gate,
wherein the first terminal of the first transis

Assignees

• Semiconductor Energy Lab

Inventors

• Ikeda Takayuki

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/115

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic

• H01L27/088 Primary

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic