Methods and devices to improve switching time by bypassing gate resistor

Patent metadata

Field	Value
Publication number	US-12231114-B2
Application number	US-202318542198-A
Country	US
Kind code	B2
Filing date	Dec 15, 2023
Priority date	Dec 12, 2016
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

First claim

The invention claimed is:

1. A switching circuit comprising:
an input terminal;
a plurality of main switches arranged in series, each main switch having a control terminal;
a common node connected to the control terminals of the main switches;
a bypass switch circuit comprising:
a first set of bypass switches arranged in series;
a second set of bypass switches arranged in series, and
a plurality of first bypass control resistors, each connected to a control terminal of a corresponding bypass switch in the first set of bypass switches, and a plurality of second bypass control resistors, each connected to a control terminal of a corresponding bypass switch in the second set of bypass switches, and
wherein:
each bypass switch in the first set is coupled to a corresponding bypass switch in the second set, and
the first set of bypass switches and the second set of bypass switches are connected between the input terminal and the common node.

2. The switching circuit of claim 1 , further comprising a plurality of main control resistors, each main control resistor connected to a corresponding control terminal of one of the main switches, the main control resistors being connected to one another at the common node.

3. The switching circuit of claim 1 , wherein the main switches are field-effect transistors (FETs).

4. The switching circuit of claim 1 , wherein the first set of bypass switches are N-type metal-oxide-semiconductor field-effect transistors (NMOS FETs), and the second set of bypass switches are P-type metal-oxide-semiconductor field-effect transistors (PMOS FETs).

5. The switching circuit of claim 4 , wherein the first set of bypass switches includes a first NMOS FET closest to the input terminal and a second NMOS FET closest to the common node, and the second set of bypass switches includes a first PMOS FET closest to the input terminal and a second PMOS FET closest to the common node.

6. The switching circuit of claim 5 , wherein drain and source terminals of the NMOS FETs are coupled with corresponding drain and source terminals of the PMOS FETs, respectively.

7. The switching circuit of claim 6 , wherein the drain terminals of the first NMOS FET and the first PMOS FET are connected together at the input terminal, and the source terminals of the second NMOS FET and the second PMOS FET are connected together at the common node.

8. The switching circuit of claim 7 , wherein the plurality of first bypass control resistors are NMOS FET gate resistors, each connected to a gate terminal of a corresponding NMOS FET, and the plurality of second bypass control resistors are PMOS FET gate resistors, each connected to a gate terminal of a corresponding PMOS FET.

9. The switching circuit of claim 8 , wherein the NMOS FET gate resistors are tied together at a first common bypass switch circuit node, and wherein the PMOS FET gate resistors are tied together at a second common bypass switch circuit node.

10. The switching circuit of claim 9 , configured to receive a first control signal at the first common bypass switch block node, and to receive a second control signal at the second common bypass switch block node.

11. The switching circuit of claim 10 , wherein the first control signal and the second control signal are configured such that:
the NMOS FETs of the common bypass switch circuit are ON when the main switches are transitioning from an OFF to an ON state, and
the PMOS FETs of the common bypass switch circuit are OFF when the main switches are transitioning from the OFF to the ON state.

12. The switching circuit of claim 11 , wherein:
the NMOS FETs of the common bypass switch circuit are OFF when the main switches are transitioning from the ON to the OFF state, and
the PMOS FETs of the common bypass switch circuit are ON when the main switches are transitioning from the ON to the OFF state.

13. The switching circuit of claim 9 , wherein the first and the second common bypass switch circuit nodes are tied to the input terminal.

14. The switching circuit of claim 13 , further comprising a first main control resistor switch arranged in parallel with a second main control resistor switch, the first and the second main control resistor switches being coupled across a corresponding main control resistor.

15. The switching circuit of claim 14 configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the main switches from an OFF to an ON state and vice versa.

16. The switching circuit of claim 15 , wherein
the first main control resistor switch is ON when the main switches are transitioning from an OFF to an ON state, and
the second main control resistor switch is OFF when the main switches are transitioning from the OFF to the ON state.

17. The switching circuit of claim 16 , wherein
the first main control resistor switch is OFF when the main switches are transitioning from the ON to the OFF state, and
the second main control resistor switch is ON when the main switches are transitioning from the ON to the OFF state.

18. The switching circuit of claim 17 , wherein the first and the second main gate resistor switches are OFF when the main FET switches are in the ON state.

19. The switching circuit of claim 18 , wherein the first main control resistor switch comprises a main bypass NMOS FET and the second main control resistor switch comprises a main bypass PMOS FET.

20. The switching circuit of claim 19 , wherein drain terminals of the main bypass NMOS and PMOS FETs are tied together, and the source terminals of the main bypass NMOS and PMOS FETs are tied together.

Assignees

• Psemi Corp

Inventors

• Shanjani Payman
• Shapiro Eric S

Classifications

• H03K17/04123 Primary

  in field-effect transistor switches · CPC title