Circuit and method for improving ESD tolerance and switching speed

Patent metadata

Field	Value
Publication number	US-9406695-B2
Application number	US-201414521378-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Nov 20, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.

First claim

What is claimed is:

1. An electronic circuit including:
a. a field effect transistor (FET) having a gate, a drain, a source, and a body;
b. a gate resistor series connected to the gate of the FET;
c. an accumulated charge sink (ACS) circuit connected to the body of the FET; and
d. an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET at a node opposite to the connection of the gate resistor to the gate.

2. The electronic circuit of claim 1 , wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit.

3. The electronic circuit of claim 1 , wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor.

4. The electronic circuit of claim 1 , wherein the ACS circuit is a diode.

5. An integrated circuit including at least two stacked field effect transistors (FET) each having a gate, a drain, a source, and a body, each FET further including:
a. a gate resistor series connected to the gate of such FET;
b. an accumulated charge sink (ACS) circuit connected to the body of such FET; and
c. an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate.

6. The integrated circuit of claim 5 , wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit.

7. The integrated circuit of claim 5 , wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor.

8. The integrated circuit of claim 5 , wherein the ACS circuit is a diode.

9. The integrated circuit of claim 5 , wherein the integrated circuit is fabricated on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.

10. A method for improving electrostatic discharge tolerance and switching speed in an integrated circuit, including:
a. fabricating an integrated circuit including a field effect transistor (FET) having a gate, a drain, a source, and a body;
b. connecting a gate resistor in series with the gate of the FET;
c. connecting an accumulated charge sink (ACS) circuit to the body of the FET;
d. connecting an ACS resistance in series with the ACS circuit; and
e. connecting the series-connected ACS resistance and the ACS circuit to the gate resistor of the FET at a node opposite to the connection of the gate resistor to the gate.

11. The method of claim 10 , further including sizing the resistance of the ACS resistance to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit.

12. The method of claim 10 , further including setting the resistance of the ACS resistance to be at least 10 times the resistance of the gate resistor.

13. The method of claim 10 , wherein the ACS circuit is a diode.

14. The method of claim 10 , wherein the step of fabricating an integrated circuit includes fabricating the integrated circuit on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.

15. An integrated circuit including at least one field effect transistor (FET) configured to switch or process a radio frequency signal, each FET having a gate, a drain, a source, and a body, each FET further including:
a. a gate resistor series connected to the gate of such FET at a first node and configured to be coupled to a control signal at a second node;
b. an accumulated charge sink (ACS) diode connected to the body of such FET; and
c. at least one ACS resistance series connected to the ACS diode, wherein the series-connected at least one ACS resistance and the ACS diode are connected to the second node, and the at least one ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS diode.

16. The integrated circuit of claim 15 , wherein the total resistance of the at least one ACS resistance has at least 10 times the resistance of the gate resistor.

17. The integrated circuit of claim 15 , wherein the integrated circuit is fabricated on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Shapiro Eric S
• Allison Matt

Classifications

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title