Analog multiplexer

Patent metadata

Field	Value
Publication number	US-9520869-B2
Application number	US-201514837279-A
Country	US
Kind code	B2
Filing date	Aug 27, 2015
Priority date	Dec 12, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A switching circuit a multiplexer includes an NMOS switch module and a PMOS switch module connected in parallel between an input and an output. A first control module powered from a first power supply voltage operates to reduce leakage currents of the NMOS switching module when in the non-conducting state. A second control module powered from a second power supply voltage operates to reduce leakage currents of the PMOS switching module when in the non-conducting state. A voltage selection circuit is configured to deliver a voltage as the second power supply voltage equal to the greater of the first power supply voltage and the voltages present at the input and at the output.

First claim

The invention claimed is:

1. A circuit, comprising:
several inputs and one output;
several switching circuits respectively connected between the inputs and the output,
wherein each switching circuit comprises:
a first switching module of the NMOS type having a conducting state and a non-conducting state; and
a second switching module of the PMOS type having a conducting state and a non-conducting state;
the first and second switching modules connected in parallel between the corresponding input and the output;
a first control module powered by a first power supply voltage and configured to reduce leakage currents of the first switching module when the first switching module is in the non-conducting state; and
a second control module powered by a second power supply voltage and configured to reducing leakage currents of the second switching module when the second switching module is in the non-conducting state; and
wherein the circuit further comprises at least one voltage selection circuit configured to deliver the second power supply voltage equal to a greater one of the first power supply voltage and of the voltages present at the input and at the output.

2. The circuit according to claim 1 , wherein the first control module and the second control module are further configured, when the first power supply voltage (Vdd) is zero, to cause the first and second switching modules to be turned off, with current consumption at the input and at the output to be zero or virtually zero.

3. The circuit according to claim 2 , wherein, when the first power supply voltage is zero, the current consumption is less than a threshold of the order of 0.1% of a normal current consumption in the presence of a first non-zero power supply voltage.

4. The circuit according to claim 1 ,
wherein the first switching module comprises two NMOS extended-drain transistors connected in series between the input and the output and having sources and substrates of the two NMOS extended-drain transistors mutually connected, and
wherein the second switching module comprises two PMOS extended-drain transistors connected in series between the input and the output and having sources and substrates of the two PMOS extended-drain transistors mutually connected.

5. The circuit according to claim 4 , wherein the first control module comprises a first control block controllable by a first binary control signal and configured, when the first binary control signal has a first logical value, to ground gates and substrates of the two NMOS transistors of the first switching module so as to place the first switching module in the non-conducting state.

6. The circuit according to claim 5 , wherein the first control module further comprises a first input block connected to the corresponding input and configured, when the first binary control signal has a second logical value corresponding to the conducting state of the first switching module, to feed control gate voltages of the two NMOS transistors of the first switching module to the voltage present at the input and limit the gate voltages to the first power supply voltage.

7. The circuit according to claim 1 , wherein the second control module is controllable by a second binary control signal and configured, when the second binary control signal has a first logical value, to bias with the second power supply voltage gates and the substrates of the two PMOS transistors of the second switching module so as to place the second switching module in the non-conducting state.

8. The circuit according to claim 7 , wherein the second control module is further configured, when the second binary control signal has a second logical value corresponding to the conducting state of the second switching module, to leave the sources and substrates of the two PMOS transistors of the second switching module floating and apply to gates of the two PMOS transistors of the second switching module a gate voltage close to the first power supply voltage.

9. The circuit according claim 7 , wherein the first control module comprises a first control block controllable by a first binary control signal, and wherein the first binary control signal and the second binary control signal are complementary signals.

10. The circuit according to claim 1 , wherein the at least one voltage selection circuit comprises a PMOS extended-drain transistor having a gate connected to a source via a resistance and powered by a current source, with the drain connected to the first power supply voltage, the source of the PMOS extended-drain transistor being connected to the input and to the output via reverse-biased diodes, respectively, the source further configured to deliver the second power supply voltage.

11. The circuit according claim 1 , implemented as an integrated circuit.

12. A circuit, comprising:
an NMOS switching module connected between an input and an output;
a PMOS switching module connected between the input and the output;
the NMOS and PMOS switching modules connected in parallel;
a first control module powered from a first power supply voltage node and configured to control a conducting state and a non-conducting state of the NMOS switching module;
a second control module powered from a second power supply voltage node and configured to control a conducting state and a non-conducting state of the PMOS switching module;
a voltage selection circuit configured to deliver a supply voltage to the second power supply voltage node equal to a greater one of the voltages at the first power supply voltage node, the input and the output.

13. The circuit according to claim 12 , wherein the voltage selection circuit comprises:
a PMOS extended-drain transistor having a gate, a source and a drain, the drain connected to the first power supply node;
a current source coupled to the gate;
a first diode coupled between the input and the source;
a second diode coupled between the output and the source; and
wherein the source is coupled to the second power supply voltage node.

14. The circuit of claim 12 , wherein the first control module is configured to reduce leakage currents of the NMOS switching module when the NMOS switching module is configured for operation in a non-conducting state between the input and output.

15. The circuit of claim 12 , wherein the second control module is configured to reduce leakage currents of the PMOS switching module when the PMOS switching module is configured for operation in a non-conducting state between the input and output.

16. The circuit according to claim 12 , wherein the first and second control modules are further configured, in response to a zero voltage at the first power supply voltage node, to cause the NMOS and PMOS switching modules to be turned off with zero current consumption at the input and output.

17. The circuit according to claim 12 , wherein the first control module is further configured to limit gate voltages of NMOS transistors within the NMOS switching module to a voltage at the first power supply voltage node.

18. A circuit, comprising:
a plurality of inputs;
an output; and
a switching circuit coupled between each input and said output, wherein each switching circuit comprises:
an NMOS switching module connected between one of the inputs and the output;
a PMOS switching module connected between said one of the inputs and the output;
the NMOS and PMOS switching modules connected in parallel;
a first control module powered from a first power supply voltage node and configured to control a conducting state and a non-

Assignees

• Stmicroelectronics (Grenoble 2) Sas

Inventors

• Fiedorow Pawel
• Masson Thierry

Classifications

• H03K17/005

  with several inputs only · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K2217/0009

  AC switches, i.e. delivering AC power to a load · CPC title