Capacitance minimization switch

US9966911B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9966911-B2
Application numberUS-201314055629-A
CountryUS
Kind codeB2
Filing dateOct 16, 2013
Priority dateOct 7, 2013
Publication dateMay 8, 2018
Grant dateMay 8, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.

First claim

Opening claim text (preview).

What is claimed is: 1. A capacitance minimization circuit, comprising: a) a CMOS transmission gate comprising signal loss caused by parasitic capacitances; and b) an amplifier circuit connected to an input of the CMOS transmission gate, wherein said amplifier circuit is configured to sense a rate of change of an input signal voltage of the CMOS transmission gate indicating a signal loss caused by the parasitic capacitances and to feed back a current according the signal loss caused by the parasitic capacitances to the input of the CMOS transmission gate in order to compensate the signal loss, wherein said amplifier circuit is an operational transconductance amplifier configured to sense the rate of change of the input signal voltage via a voltage drop across a resistor of an RC network, comprising the resistor and a capacitor connected in series, wherein the RC network is connected between the input of the CMOS transmission gate and ground, wherein the operational transconductance amplifier is further configured to provide an output current to the input of the CMOS transmission gate to compensate the signal loss due to the parasitic capacitances. 2. The circuit of claim 1 , wherein said operational transconductance amplifier forms a part of a positive feedback loop, wherein the loop gain is set to be less than one. 3. A method of capacitance minimization, comprising: a) forming a CMOS transmission gate with an N-channel transistor connected in parallel with a P-channel transistor between an input and an output; and b) connecting an amplifier in series to the input of the CMOS transmission gate in order to implicitly or explicitly sense a rate of change of an input signal voltage of the CMOS transmission gate indicating a signal loss caused by parasitic capacitances of the CMOS transmission gate and to feed back a current according to the signal loss caused by the parasitic capacitance of the CMOS transmission gate to an input of the CMOS transmission gate in order to compensate the signal loss, wherein the amplifier is a transconductance amplifier capable of sensing the rate of change of the input signal voltage by sensing a voltage drop across a resistor of a RC network, comprising a resistor and a capacitor connected in series, wherein the RC network is connected between the input of the CMOS transmission gate and ground, wherein the operational transconductance amplifier is further configured to provide an output current to the input of the CMOS transmission gate to compensate the signal loss due to the parasitic capacitances. 4. The circuit of claim 1 , wherein said operational transconductance amplifier has a gain of less than 1. 5. The method of claim 3 , wherein said amplifier has a gain of less than 1.

Assignees

Inventors

Classifications

  • in field-effect transistor switches · CPC title

  • using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

  • Gating switches, e.g. pass gates · CPC title

  • H03K17/145Primary

    in field-effect transistor switches · CPC title

  • with FET's · CPC title

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What does patent US9966911B2 cover?
A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the result…
Who is the assignee on this patent?
Dialog Semiconductor Gmbh
What technology area does this patent fall under?
Primary CPC classification H03F3/45179. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 08 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).