Switch circuit and SPDT switch circuit

Patent metadata

Field	Value
Publication number	US-9705492-B2
Application number	US-201314140035-A
Country	US
Kind code	B2
Filing date	Dec 24, 2013
Priority date	Dec 26, 2012
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

The present invention relates to a switch circuit and a single pole double throw (SPDT) circuit. The switch circuit includes: a MOS transistor transferring or blocking a signal according to a turn on/off operation thereof; a gate resistor connected to a gate of the MOS transistor; and a variable gate resistor circuit increasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-off state to a turn-on state.

First claim

What is claimed is:

1. An SPDT circuit comprising:
an antenna;
a first MOS transistor group transmitting a transmission signal from a transmitting end to the antenna according to a turn-on operation thereof and blocking introduction of a reception signal received in the antenna into the transmitting end according to a turn-off operation thereof;
a first gate resistor group including gate resistors each connected to gates of the respective transistors of the first MOS transistor group;
a second MOS transistor group applied with gate power complementary to turn-on gate power of the first MOS transistor group to operate complementarily to the first MOS transistor group, transferring the reception signal to a receiving end, and blocking leakage of the transmission signal to the receiving end;
a second gate resistor group including gate resistors each connected to gates of the respective transistors of the second MOS transistor group; and
a variable gate resistor circuit group increasing resistance values of the respective gate resistors when each of the first and second MOS transistor groups is changed from a turn-off state to a turn-on state.

2. The SPDT circuit according to claim 1 , wherein the variable gate resistor circuit group includes a first variable gate resistor circuit increasing the resistance values of the respective gate resistors when the first MOS transistor group is changed from a turn-off state to a turn-on state; and a second variable gate resistor circuit increasing the resistance values of the respective gate resistors when the second MOS transistor group is changed from a turn-off state to a turn-on state,
the first variable gate resistor circuit including a first series additional resistor; a first transistor turned on at the time of applying turn-on gate power of the first MOS transistor group to connect the first series additional resistor in series with the respective gate resistors of the first MOS transistor group, thereby increasing the resistances value of the gate resistors; and a second transistor connected in parallel with the first transistor and turned on at the time of applying turn-off gate power of the first MOS transistor group to turn off the first MOS transistor group, and
the second variable gate resistor circuit including a second series additional resistor; an eleventh transistor turned on at the time of applying turn-on gate power of the second MOS transistor group to connect the second series additional resistor in series with the respective gate resistors of the second MOS transistor group, thereby increasing the resistances value of the gate resistors; and a twelfth transistor connected in parallel with the eleventh transistor and turned on at the time of applying turn-off gate power of the second MOS transistor group to turn off the second MOS transistor group.

3. The SPDT circuit according to claim 2 , wherein in each of the first and second MOS transistor groups, NMOS transistors are connected to one another in a cascode structure, and
each of the first, second, eleventh, and twelfth transistors is an NMOS transistor.

4. The SPDT circuit according to claim 2 , wherein in each of the first and second MOS transistor groups, NMOS transistors are connected to one another in a cascode structure,
each of the first and eleventh transistors is an NMOS transistor, and
each of the second and twelfth transistors is a PMOS transistor.

Assignees

• Samsung Electro Mech

Inventors

• Choi Jae Hyouck
• Park Sung Hwan

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• Y10T307/747

  Cross-Sectional Technologies · mapped topic

• H03K17/51

  characterised by the components used (H03K17/04 - H03K17/30, H03K17/94 take precedence) · CPC title

• H04B1/00

  Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission · CPC title

• H04B1/48

  in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} · CPC title