Three-dimensional memory devices and methods for forming the same

US12148714B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12148714-B2
Application numberUS-202117488846-A
CountryUS
Kind codeB2
Filing dateSep 29, 2021
Priority dateSep 13, 2021
Publication dateNov 19, 2024
Grant dateNov 19, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure containing a core region and a staircase region, a channel structure extending through the stack structure in the core region, and a first support structure extending through the stack structure in the staircase region. The first support structure includes a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A three-dimensional (3D) memory device, comprising: a stack structure comprising a core region and a staircase region; a channel structure extending through the stack structure in the core region; and a first support structure extending through the stack structure in the staircase region, wherein the first support structure comprises a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction, wherein the second portion of the first support structure comprises a first plurality of curved portions protruding from a first side of the first portion and a second plurality of curved portions protruding from a second side of the first portion at predetermined intervals along its length, wherein a curvature of each of the first plurality of curved portions and the second plurality of curved portions contacts the first portion, and wherein the first support structure is located between two blocks of the 3D memory device. 2. The 3D memory device of claim 1 , further comprising a second support structure, wherein the second support structure comprises a set of block shape support structures arranged in a two-dimensional array. 3. The 3D memory device of claim 2 , wherein the second support structure is located within a same memory block. 4. The 3D memory device of claim 2 , wherein at least one of the block shape support structures has one of a square shape, a rectangular shape, or a L-shape. 5. The 3D memory device of claim 1 , wherein the first plurality of curved portions and the second plurality of curved portions are aligned along two opposite sides of the first portion of the first support structure pair-by-pair. 6. The 3D memory device of claim 1 , wherein adjacent two curved portions of the first plurality of curved portions or the second plurality of curved portions have a same distance therebetween along the first direction. 7. The 3D memory device of claim 1 , wherein a radius of a curved portion is between ¼ of a width of the first portion in the second direction and two times of the width of the first portion in the second direction. 8. The 3D memory device of claim 1 , wherein a distance between edges of adjacent two curved portions of the first plurality of curved portions or the second plurality of curved portions is between ⅙ of a width of the first portion in the second direction and three times of the width of the first portion in the second direction. 9. The 3D memory device of claim 1 , wherein each of the first plurality of curved portions and the second plurality of curved portions has a same shape. 10. The 3D memory device of claim 1 , wherein each of the first plurality of curved portions and the second plurality of curved portions has a shape of a partial of a circle. 11. The 3D memory device of claim 1 , wherein each of the first plurality of curved portions and the second plurality of curved portions has a shape of a partial of an ellipse. 12. The 3D memory device of claim 1 , further comprises a plurality of gate line slits intermittently extending along the first direction, wherein the plurality of gate line slits are located in a same memory block of the 3D memory device. 13. A method for forming a three-dimensional (3D) memory device, comprising: forming a stack structure, the stack structure comprising a core region and a staircase region; forming a channel structure extending through the stack structure in the core region; and forming a first support structure extending through the stack structure in the staircase region, wherein the first support structure has a bead-embedded strip shape in a plan view, wherein the bead-embedded strip shape is a shape comprising one elongated center strip shape extending along a first direction and embedded with a plurality of beads extending from a second direction at predetermined intervals along the elongated center strip shape, wherein a curvature of each of the plurality of beads contacts the elongated center strip shape, and wherein a plurality of seams are formed inside or on a surface of the first support structure along the first direction. 14. The method of claim 13 , wherein forming the first support structure further comprises: forming an elongated trench through the stack structure in the staircase region, wherein the elongated trench comprises a plurality of curved portions protruding from two opposite sides of an elongated slit; and filling in the elongated trench with an insulation material to form the first support structure. 15. The method of claim 14 , wherein the elongated trench is etched in places of the stack structure between adjacent two blocks of the 3D memory device. 16. The method of claim 13 , further comprising: forming a second support structure, wherein the second support structure comprises a set of block shape support structures arranged in a two-dimensional array. 17. A system, comprising: a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stack structure comprising a core region and a staircase region, a channel extending through the stack structure in the core region, and a first support structure extending through the stack structure in the staircase region, wherein the first support structure has a bead-embedded strip shape in a plan view, wherein the bead-embedded strip shape is a shape comprising one elongated center strip shape extending along a first direction and embedded with a plurality of beads extending from a second direction at predetermined intervals along the elongated center strip shape, wherein a curvature of each of the plurality of beads contacts the elongated center strip shape, and wherein the first support structure is located between two blocks of the 3D memory device; and a memory controller coupled to the 3D memory device and configured to control the 3D memory device.

Assignees

Inventors

Classifications

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • Vias, e.g. via plugs · CPC title

  • H10W42/121Primary

    protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

  • H10B43/27Primary

    the channels comprising vertical portions, e.g. U-shaped channels · CPC title

  • the channels comprising vertical portions, e.g. U-shaped channels · CPC title

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What does patent US12148714B2 cover?
Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure containing a core region and a staircase region, a channel structure extending through the stack structure in the core region, and a first support structure extending through the stack structure in the staircase region. The first support structu…
Who is the assignee on this patent?
Yangtze Memory Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 19 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).