Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2018277556-A1
Application number	US-201715788476-A
Country	US
Kind code	A1
Filing date	Oct 19, 2017
Priority date	Mar 21, 2017
Publication date	Sep 27, 2018
Grant date	—

Abstract

Provided herein may be a semiconductor device. The semiconductor device may include a stack, channel holes passing through the stack, dummy channel holes passing through the stack and disposed between the channel holes, a slit passing through the stack and the dummy channel holes.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a stack; channel holes passing through the stack; dummy channel holes passing through the stack and disposed between the channel holes; a slit passing through the stack and overlapping with the dummy channel holes to integrally couple the dummy channel holes with the slit; channel layers formed in the channel holes; and dummy channel layers including first semiconductor patterns formed in the dummy channel holes, and second semiconductor patterns formed in the slit and coupling the first semiconductor patterns with each other.

2 . The semiconductor device according to claim 1 ,
wherein the channel holes include memory layers enclosing the respective channel layers, and wherein the dummy channel holes and the slit include dummy memory layers enclosing the respective dummy channel layers.

3 . The semiconductor device according to claim 1 , wherein the stack comprises stacked word lines, and select lines disposed over the word lines, and the slit has a depth at which the select lines are separated from each other by the slit.

4 . The semiconductor device according to claim 1 ,
wherein the dummy channel hole has a first width and the slit has a second width, and wherein the second width is less than the first width.

5 . The semiconductor device according to claim 1 , further comprising:
gap fill insulating layers formed in the respective channel layers; and dummy gap fill insulating layers formed in the respective first semiconductor patterns of the dummy channel layers.

6 . The semiconductor device according to claim 1 , further comprising:
gap fill insulating layers formed in the respective channel layers; first dummy gap fill insulating patterns formed in the respective first semiconductor patterns of the dummy channel layers; and second dummy gap fill insulating patterns formed in the respective second semiconductor patterns of the dummy channel layers and coupling the first dummy gap fill insulating patterns with each other.

7 . The semiconductor device according to claim 1 , wherein the first and second semiconductor patterns comprise semiconductor material.

8 . A semiconductor device comprising:
a stack; a channel layer passing through the stack to a first depth; and a dummy channel layer comprising first semiconductor patterns passing through the stack to the first depth, and second semiconductor patterns passing through the stack to a second depth less than the first depth and coupling the first semiconductor patterns with each other.

9 . The semiconductor device according to claim 8 , further comprising:
a memory layer enclosing the channel layer; a dummy memory layer enclosing the dummy channel layer; a gap fill insulating layer formed in the channel layer; and dummy gap fill insulating layers formed in the respective first semiconductor patterns of the dummy channel layer.

10 . The semiconductor device according to claim 8 , further comprising:
a memory layer enclosing the channel layer; a dummy memory layer enclosing the dummy channel layer; a gap fill insulating layer formed in the channel layer; first dummy gap fill insulating patterns formed in the respective first semiconductor patterns of the dummy channel layer; and second dummy gap fill insulating patterns formed in the respective second semiconductor patterns of the dummy channel layer and coupling the first dummy gap fill insulating patterns with each other.

11 . The semiconductor device according to claim 8 , further comprising:
a memory layer enclosing the channel layer; a dummy memory layer enclosing the dummy channel layer;

12 . The semiconductor device according to claim 8 , wherein the stack comprises stacked word lines, and select lines disposed over the word lines, and each of the second semiconductor patterns has a depth at which the second semiconductor pattern passes through the select lines.

13 . The semiconductor device according to claim 8 , wherein each of the first semiconductor patterns has a first width and each of the second semiconductor patterns has a second width, and
wherein the second width is less than the first width.

14 . A semiconductor device comprising:
a stack; channel layers passing through the stack; and a slit insulating layer disposed between the channel layers, and comprising a semiconductor pattern passing through the stack and extending in a first direction, and an insulating pattern enclosing the semiconductor pattern.

15 . The semiconductor device according to claim 14 , wherein the slit insulating layer passes through a portion of the stack.

16 . The semiconductor device according to claim 14 , wherein the semiconductor pattern in the slit insulating layer is in a floating state.

Assignees

• Sk Hynix Inc

Inventors

• Kang Byung Woo

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L27/11565

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L21/76224

  Electricity · mapped topic