Three-dimensional memory device having conductive support structures and method of making thereof

Patent metadata

Field	Value
Publication number	US-2018301374-A1
Application number	US-201715489050-A
Country	US
Kind code	A1
Filing date	Apr 17, 2017
Priority date	Apr 17, 2017
Publication date	Oct 18, 2018
Grant date	—

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a horizontal layer, which can be formed over a lower-interconnect-level dielectric material layer overlying a substrate. Structural integrity of insulating layers vertically spaced from one another by backside recesses during replacement of sacrificial material layers with electrically conductive layers can be enhanced by forming electrically inactive laterally-insulated support structures concurrently with formation of laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer and to lower-interconnect-level metal interconnect structures. Alternatively or additionally, the structural integrity of insulating layers during the replacement process can be enhanced by M×N array of semiconductor-containing support structures that extend through staircase region and having same materials as memory stack structures.

First claim

1 . A three-dimensional memory device comprising:
a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures; a horizontal layer overlying the lower-interconnect-level dielectric material layer; an alternating stack of insulating layers and electrically conductive layers located over the horizontal layer; an array of memory stack structures extending through the alternating stack; laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core; and laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer wherein: the alternating stack includes a staircase region in which each electrically conductive layer except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack; a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion.

2 . The three-dimensional memory device of claim 1 , wherein each first conductive core contacts a bottom surface of a respective one of upper-interconnect-level metal interconnect structures that are embedded within the overlying upper-interconnect-level dielectric material layer.

3 . The three-dimensional memory device of claim 1 , wherein a bottommost surface of each second conductive core is located between a first horizontal plane including a bottommost surface of the horizontal layer and a second horizontal plane including a topmost surface of the horizontal layer.

4 . The three-dimensional memory device of claim 1 , wherein:
a bottommost surface of each second conductive core contacts a respective metallic material portion embedded within the lower-interconnect-level dielectric material layer; and each second conductive core is electrically isolated from any conductive or semiconducting material within the substrate, the horizontal layer, the alternating stack, or upper-interconnect-level metal interconnect structures located over the alternating stack.

5 . (canceled)

6 . The three-dimensional memory device of claim 1 , further comprising:
contact via structures vertically extending from a top surface of the retro-stepped dielectric material portion to a respective region of the multiple sets of stepped surfaces and contacting a respective one of the electrically conductive layers, wherein a subset of horizontal surfaces within one set among the multiple sets of stepped surfaces includes a respective horizontal surface including a first opening through which a respective one of the contact via structures extends vertically and a second opening through which a respective one of the laterally-insulated support structures extends vertically; and backside trenches laterally extending along a horizontal direction and vertically extending through an entirety of the alternating stack, wherein each set of stepped surfaces is laterally bounded by a neighboring pair of the backside trenches.

7 . The three-dimensional memory device of claim 6 , wherein a complementary subset of horizontal surfaces within the one set among the multiple sets of stepped surfaces includes openings through which a respective one of the laterally-insulated support structures extend vertically, and does not contact any of the contact via structures, wherein the complementary subset of horizontal surfaces and the set of horizontal surfaces collectively comprise all horizontal surfaces of the one set among the multiple sets of stepped surfaces.

8 . The three-dimensional memory device of claim 6 , further comprising semiconductor-containing support structures extending through the multiple sets of stepped surfaces, wherein:
each semiconductor-containing support structure and each memory stack structure comprises a respective instance of a memory film and a respective instance of a vertical semiconductor channel that is laterally surrounded by the respective instance of the memory film and contacts a bottom surface of a respective instance of a drain region; and each horizontal surface within the multiple sets of stepped surfaces includes at least one opening through which a respective one of the semiconductor-containing support structures extends vertically.

9 . The three-dimensional memory device of claim 6 , wherein:
electrically conductive layers comprise word lines extending in a word line direction; and each row extending in the word line direction contains alternating laterally-insulated conductive via structures and laterally-insulated support structures.

10 . The three-dimensional memory device of claim 6 , wherein the contact via structures vertically extend in a first-type contact via region and a second-type contact via region having a two-fold rotational symmetry around a vertical axis.

11 . The three-dimensional memory device of claim 1 , wherein:
the substrate comprises a semiconductor substrate; the horizontal layer comprises an electrically conductive buried source line; each memory stack structure within the array includes a vertical semiconductor channel electrically connected to the horizontal layer; and a driver circuit for the array of memory stack structures is located on a top surface of the semiconductor substrate and is electrically connected to at least one of the electrically conductive layers in the alternating stack and drain regions overlying vertical semiconductor channels within the memory stack structures through a subset of the lower-interconnect-level metal interconnect structures.

12 . The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device; the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device; the substrate comprises a silicon substrate; the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; the electrically conduc

Assignees

• Sandisk Technologies Llc

Inventors

• Masamori Yohei
• Ogawa Hiroyuki

Classifications

• H01L23/5226

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic