Three-dimensional memory device containing support pillars underneath a retro-stepped dielectric material and method of making thereof

Patent metadata

Field	Value
Publication number	US-10141331-B1
Application number	US-201715607583-A
Country	US
Kind code	B1
Filing date	May 29, 2017
Priority date	May 29, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region and a terrace region;
memory stack structures extending through the memory array region of the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel contacting an inner sidewall of the respective memory film; and
support pillar structures extending through the terrace region of the alternating stack,
wherein the support pillar structures have different heights from each other;
wherein each of the support pillar structures has a respective topmost surface that is coplanar with a top surface of a respective one of the insulating layers in the alternating stack; and
wherein each of the support pillar structures comprises a dummy vertical semiconductor channel that is identical to the vertical semiconductor channels in material composition.

2. The three-dimensional memory device of claim 1 , wherein:
each layer of the alternating stack is present in the memory array region;
in the terrace region, each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack; and
at least some of the support pillar structures has a respective topmost surface that is more proximal to a top surface of the substrate than topmost surfaces of the memory stack structures are to the top surface of the substrate.

3. The three-dimensional memory device of claim 2 , further comprising an insulating cap layer overlying the alternating stack, wherein the topmost surface of the memory stack structures are coplanar with a top surface of the insulating cap layer.

4. The three-dimensional memory device of claim 1 , wherein:
bottommost surfaces of the support pillar structures are within a first horizontal plane; and
topmost surfaces of the support pillar structures are within a respective one of multiple horizontal planes.

5. The three-dimensional memory device of claim 1 , wherein:
the electrically conductive layers comprise word lines;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
a retro-stepped dielectric material portion contacts the stepped surfaces and overlies the support pillar structures.

6. The three-dimensional memory device of claim 5 , wherein:
topmost surfaces of the support pillar structures contact a respective one of multiple horizontal bottom surfaces of the retro-stepped dielectric material portion; and
bottom surfaces of the retro-stepped dielectric material portion contact topmost surfaces of the support pillar structures and top surfaces of the insulating layers such that the support pillar structures do not extend into the retro-stepped dielectric material portion.

7. The three-dimensional memory device of claim 5 , further comprising word line contact via structures which extend through the retro-stepped dielectric material portion and contact top surfaces of the word lines in the terrace region.

8. The three-dimensional memory device of claim 1 , wherein each of the support pillar structures comprises
a dummy memory film that is identical to the memory films of the memory stack structures in material composition.

9. The three-dimensional memory device of claim 8 , wherein:
a top end of each vertical semiconductor channel contacts a respective drain region; and
a top end of each dummy vertical semiconductor channel contacts a respective dummy drain region having a same composition as the drain regions.

10. The three-dimensional memory device of claim 9 , wherein:
each top surface of the drain regions is contacted by a bottom surface of a respective drain contact via structure; and
each top surface of the dummy drain regions is contacted by a retro-stepped dielectric material portion.

11. The three-dimensional memory device of claim 8 , wherein:
each of the memory stack structures contacts a respective underlying pedestal channel portion; and
each of the support pillar structures comprises a respective dummy pedestal channel portion that underlies a respective dummy memory film and having a same composition as the pedestal channel portions.

12. The three-dimensional memory device of claim 11 , wherein each of the underlying pedestal channel portion and each of the underlying dummy pedestal channel portion comprise a single crystalline semiconductor material in epitaxial alignment with a single crystalline semiconductor material of a semiconductor material layer located in the substrate.

13. The three-dimensional memory device of claim 12 , wherein:
each of the underlying pedestal channel portion and each of the underlying dummy pedestal channel portion are laterally surrounded by a respective tubular dielectric spacer; and
each of the tubular dielectric spacers is laterally surrounded by a bottommost one of the electrically conductive layers.

14. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

15. The three-dimensional memory device of claim 1 , wherein:
top surfaces of the memory stack structures are located above a horizontal plane including a top surface of a topmost one of the electrically conductive layers; and
each top surface of the support pillar structures is located below the horizontal plane including the top surface of the topmost one of the electrically conductive layers.

16. The three-dimensional memory device of claim 1 , further comprising a retro-stepped dielectric material portion contacting each top surface of the support pillar structures.

17. The three-dimensional memory device of claim 16 , wherein a top surface of the re

Assignees

• Sandisk Technologies Llc

Inventors

• Susuki Hiromasa
• Tsutsumi Masanori
• Inoue Shigehisa
• Oh Junji
• Yamaguchi Kensuke
• Shimabukuro Seiji
• Fukano Yuji
• EHARA Ryoichi
• FURIHATA Youko

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H10B43/10 Primary

  characterised by the top-view layout · CPC title