Memory device and method for fabricating the memory device

Patent metadata

Field	Value
Publication number	US-2020152585-A1
Application number	US-201916459796-A
Country	US
Kind code	A1
Filing date	Jul 2, 2019
Priority date	Nov 9, 2018
Publication date	May 14, 2020
Grant date	—

Abstract

A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.

First claim

What is claimed is:

1 . A vertical memory device, comprising:
a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters coupled between the pad portions of the gate electrodes and the substrate.

2 . The vertical memory device of claim 1 , wherein at least one of the pad portions is coupled to the substrate through two or more supporters, the two or more supporters comprising a dielectric material.

3 . The vertical memory device of claim 1 , wherein for each of the pad portions that are coupled to the substrate through two or more supporters and are coupled to a contact plug from the plurality of contact plugs, a first supporter from the two or more supporters vertically overlaps with the contact plug and a second supporter from the two or more supporters is spaced apart from the first supporter.

4 . The vertical memory device of claim 1 , wherein each of the supporters extend substantially perpendicular from a surface of the substrate to couple with a gate electrode from the plurality of gate electrodes.

5 . The vertical memory device of claim 1 , wherein upper surfaces of two or more supporters coupled between a surface of the substrate and a gate electrode from the plurality of gate electrodes have different heights from the surface of the substrate.

7 . The vertical memory device of claim 1 , wherein a bottom surface of each of the supporters contacts a surface of the substrate.

8 . The vertical memory device of claim 1 , wherein a cross-sectional area of each of the supporters coupled to a pad portion from the plurality of pad portions is greater than a cross-sectional area of a contact plug, from the plurality of contact plugs, coupled to the pad portion.

9 . The vertical memory device of claim 1 , further comprising:
a plurality of dielectric layers formed between the gate electrodes.

10 . The vertical memory device of claim 9 , wherein the dielectric layers and the supporters are formed of substantially the same material.

11 . The vertical memory device of claim 1 , further comprising:
a plurality of vertical channel structures penetrating through the gate electrodes that are stacked in the memory cell region.

12 . The vertical memory device of claim 1 , wherein a cross-section of each of the supporters has substantially a circular, an elliptical, or polygonal shape.

13 . A vertical memory device, comprising:
a substrate including a first region and a second region; a plurality of horizontal dielectric layers and a plurality of horizontal conductive layers that extend from the first region to the second region and have end portions stacked in a step shape in the second region; a plurality of vertical conductive layers that are coupled to the end portions of the horizontal conductive layers; and at least a pair of dielectric supporters that are formed below each of the end portions of the horizontal conductive layers and penetrate through the horizontal dielectric layers.

14 . The vertical memory device of claim 13 , wherein each of the pairs of supporters includes a first supporter that vertically overlaps with the vertical conductive layer and a second supporter that is spaced apart from the first supporter and does not vertically overlap with the vertical conductive layer.

15 . The vertical memory device of claim 13 , wherein each of the pairs of supporters extend substantially perpendicular from a surface of the substrate.

16 . The vertical memory device of claim 13 , wherein the horizontal conductive layers and the vertical conductive layers include a metallic material.

17 . The vertical memory device of claim 13 , wherein the horizontal dielectric layers and the supporters include an oxide.

18 . The vertical memory device of claim 13 , further comprising:
a plurality of conductive vertical structures that penetrate through the horizontal conductive layers and the horizontal dielectric layers in the first region.

19 . The vertical memory device of claim 13 , wherein the first region is a memory cell region and the second region is a contact region.

Assignees

• Sk Hynix Inc

Inventors

• Eom Dae-Sung

Classifications

• H01L23/5283

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic