Metrology target design for tilted device designs

Patent metadata

Field	Value
Publication number	US-12117347-B2
Application number	US-201615287388-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Apr 21, 2015
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

Metrology methods, modules and targets are provided, for measuring tilted device designs. The methods analyze and optimize target design with respect to the relation of the Zernike sensitivity of pattern placement errors (PPEs) between target candidates and device designs. Monte Carlo methods may be applied to enhance the robustness of the selected target candidates to variation in lens aberration and/or in device designs. Moreover, considerations are provided for modifying target parameters judiciously with respect to the Zernike sensitivities to improve metrology measurement quality and reduce inaccuracies.

First claim

What is claimed is:

1. A method comprising:
calculating, with at least one processor, a Zernike sensitivity of pattern placement errors (PPEs) of at least one device design and of a plurality of metrology target designs;
selecting, with at least one processor, a best metrology target design according to a value of a cost function derived from the calculated Zernike sensitivities, the cost function quantifying a similarity of the Zernike sensitivity between the at least one device design and the plurality of metrology target designs;
controlling, with at least one processor, a scanner to modify a pattern pitch to produce one or more metrology targets having the best metrology target design on a sample; and
performing, with an overlay metrology tool, one or more overlay metrology measurements of the one or more metrology targets having the best metrology target design.

2. The method of claim 1 , wherein the Zernike sensitivity is calculated with respect to Zernike coefficients Z4 . . . Z36.

3. The method of claim 2 , wherein the Zernike sensitivity is calculated with respect to odd Zernike coefficients only.

4. The method of claim 3 , wherein the Zernike sensitivity is calculated only with respect to Zernike coefficients Z8, Z11, Z15, Z20, Z24, Z27, Z31, and Z35.

5. The method of claim 1 , wherein the cost function comprises a distance metric between the PPE Zernike sensitivity of the at least one device design and the PPE Zernike sensitivity of the plurality of metrology target designs.

6. A metrology module comprising at least one computer processor configured to:
calculate a Zernike sensitivity of pattern placement errors (PPEs) of at least one device design and of a plurality of metrology target designs;
select a best metrology target design according to a value of a cost function derived from the calculated Zernike sensitivities, the cost function quantifying a similarity of the Zernike sensitivity between the at least one device design and the plurality of metrology target designs;
control a scanner to modify a pattern pitch to produce one or more metrology targets having the best metrology target design on a sample; and
perform, with an overlay metrology tool, one or more overlay metrology measurements of the one or more metrology targets having the best metrology target design.

7. The metrology module of claim 6 , wherein the Zernike sensitivity is calculated with respect to Zernike coefficients Z4 . . . Z36.

8. The metrology module of claim 7 , wherein the Zernike sensitivity is calculated with respect to odd Zernike coefficients only.

9. The metrology module of claim 8 , wherein the Zernike sensitivity is calculated only with respect to Zernike coefficients Z8, Z11, Z15, Z20, Z24, Z27, Z31, and Z35.

10. The metrology module of claim 6 , wherein the cost function comprises a distance metric between the PPE Zernike sensitivity of the at least one device design and the PPE Zernike sensitivity of the plurality of metrology target designs.

11. A method comprising:
for each of at least one device design and a plurality of target design candidates:
repeatedly for a plurality of runs:
generating, with at least one processor, a plurality of N i (N i >50) Zernike coefficient values for each of a plurality of Zernike polynomials Z i , the values generated pseudo-randomly with respect to specified distributions over specified ranges,
calculating, with at least one processor, PPEs for each of the Zernike polynomials, and
calculating, with at least one processor, a respective PPE measure for the run; and

deriving, with at least one processor, a distribution of the calculated respective PPE measures;

correlating, with at least one processor, each of the derived target design candidate distributions with the at least one derived device design distribution to yield for each target design candidate a device correspondence measure; and
selecting, with at least one processor, a best metrology target design according to the derived device correspondence measures;
controlling, with at least one processor, a scanner to modify a pattern pitch to produce one or more metrology targets having the best metrology target design on a sample; and
performing, with an overlay metrology tool, one or more overlay metrology measurements of the one or more metrology targets having the best metrology target design.

12. The method of claim 11 , further comprising selecting the target design candidates to represent segmentation alternatives of a specified target design.

13. The method of claim 12 , further comprising ranking the segmentation alternatives using the device correspondence measure.

14. The method of claim 11 , further comprising carrying out the calculating stages in parallel to a metrology simulation process and integrating a ranking using the device correspondence measure with a ranking derived from the metrology simulation process.

15. The method of claim 11 , further comprising carrying out the method for multiple device designs and carrying out the selecting with respect to the device correspondence measures derived for all the device designs.

16. The method of claim 15 , wherein the selecting is carried out with respect to a robustness measure, derived from the multiple device correspondence measures.

17. A metrology module comprising at least one computer processor configured to, for each of at least one device design and a plurality of target design candidates:
repeatedly for a plurality of runs:
generate, with at least one processor, a plurality of N i (N i >100) Zernike coefficient values for each of a plurality of Zernike polynomials Z i , the values generated pseudo-randomly with respect to specified distributions over specified ranges,
calculate, with at least one processor, PPEs for each of the Zernike polynomials, and
calculate, with at least one processor, a respective PPE measure for the run; and

derive, with at least one processor, a distribution of the calculated respective PPE measures;
correlate, with at least one processor, each of the derived target design candidate distributions with the at least one derived device design distribution to yield for each target design candidate a device correspondence measure;
select, with at least one processor, a best metrology target design according to the derived device correspondence measures;
controlling, with at least one processor, a scanner to modify a pattern pitch to produce one or more metrology targets having the best metrology target design on a sample; and
performing, with an overlay metrology tool, one or more overlay metrology measurements of the one or more metrology targets having the best metrology target design.

18. The metrology module of claim 17 , further configured to select the target design candidates to represent segmentation alternatives of a specified target design.

19. The metrology module of claim 18 , further configured to rank the segmentation alternatives using the device correspondence measure.

20. The metrology module of claim 17 , further configured to carry out the calculating stages in parallel to a metrology simulation process and to integrate a ranking using the device correspondence measure with a ranking derived from the metrology simulation process.

21. The metrology module of claim 17 , further configured to use multiple device designs and select the best target with respect to the device correspondence measures derived for all the device designs.

22. The metrolo

Assignees

• Kla Corp

Inventors

• Lee Myungjun
• Smith Mark D
• Adel Michael E
• Amit Eran
• Kandel Daniel

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G03F7/70683 Primary

  Mark designs · CPC title

• G03F7/70591

  Testing optical components · CPC title

• G01J9/00 Primary

  Measuring optical phase difference (devices or arrangements for controlling the phase of light beams G02F1/01); Determining degree of coherence; Measuring optical wavelength (spectrometry G01J3/00) · CPC title