Method and apparatus for design of a metrology target

Patent metadata

Field	Value
Publication number	US-9355200-B2
Application number	US-201414577820-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 30, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A method of metrology target design is described. The method includes determining a sensitivity of a parameter for a metrology target design to an optical aberration, determining the parameter for a product design exposed using an optical system of a lithographic apparatus, and determining an impact on the parameter of the metrology target design based on the parameter for the product design and the product of the sensitivity and one or more of the respective aberrations of the optical system.

First claim

What is claimed is:

1. A method of metrology target structure design, the method comprising:
determining a value of a sensitivity of a parameter for a design of a metrology target structure to an optical aberration, wherein the metrology target structure is used for metrology in the manufacture of physical devices;
determining, by a hardware computer system, an impact on the parameter of the metrology target structure design based on the parameter for a device product design exposed using an optical system of a lithographic apparatus and based on a value that is equivalent to the value of the sensitivity multiplied by a value of a respective optical aberration of the optical system.

2. The method of claim 1 , comprising determining a value of a sensitivity of a parameter for a metrology target structure design to each of a plurality of optical aberrations and determining an impact on the parameter of the metrology target structure design based on the parameter for the device product design and based on one or more values that are equivalent to the values of the sensitivities multiplied by values of respective optical aberrations of the optical system.

3. The method of claim 1 , further comprising determining the parameter for the device product design exposed using the optical system of the lithographic apparatus.

4. The method of claim 3 , further comprising determining the parameter for the device product design by simulating the device product design as exposed using the optical system.

5. The method of claim 1 , wherein determining the value of the sensitivity is performed by simulation using a lithographic model.

6. The method of claim 1 , wherein the parameter of the metrology target structure design comprises an overlay error.

7. The method of claim 1 , wherein the optical aberration comprises a Zernike polynomial.

8. The method of claim 1 , wherein determining the impact comprises summation, for a plurality of positions of an exposure slit of the lithographic apparatus, of values that are equivalent to the value of the sensitivity multiplied by a value of the respective optical aberration of the optical system.

9. The method of claim 1 , wherein the sensitivity is considered to be linear within a design range of the optical system aberration variations.

10. The method of claim 1 , comprising performing the determining for a plurality of different metrology target structure designs to identify a metrology target structure design with a smallest difference between the parameter for the metrology target structure design and the parameter for the device product design.

11. A method of metrology target structure design, the method comprising:
determining a value of a sensitivity of overlay error of a design of a metrology target structure to each respective aberration of a plurality of aberrations, wherein the metrology target structure is used for metrology in the manufacture of physical devices; and
determining, by a hardware computer system, an impact of the metrology target structure design on overlay error based on a sum of values that are equivalent to the values of the sensitivities multiplied by values of respective aberrations of an optical system of a lithographic apparatus used to expose the metrology target structure.

12. The method of claim 11 , wherein the aberrations respectively comprise a Zernike polynomial.

13. The method of claim 11 , wherein the sensitivities are considered to be linear within a design range of the optical system aberration variations.

14. The method of claim 11 , wherein determining the values of the sensitivity is performed by simulation using a lithographic model.

15. The method of claim 11 , further comprising simulating an overlay error of a device product design exposed using the optical system.

16. The method of claim 11 , wherein determining the impact comprises summation, for a plurality of positions of an exposure slit of the lithographic apparatus, of values that are equivalent to the values of the sensitivities multiplied by values of respective optical aberrations of the optical system.

17. A computer readable medium comprising instructions executable by a computer to perform a method according to claim 1 .

18. A computer readable medium comprising instructions executable by a computer to perform a method according to claim 11 .

19. The method of claim 1 , further comprising selecting the metrology target structure design based on the impact and measuring the metrology structure of the selected metrology target design in the manufacture of physical devices.

20. The method of claim 11 , further comprising selecting the metrology target structure design based on the impact and measuring the metrology structure of the selected metrology target design in the manufacture of physical devices.

Assignees

• Asml Netherlands Bv

Inventors

• Chen Guangqing
• Kent Eric Richard
• Wang Jen-Shiang
• Adam Omer Abubaker Omer

Classifications

• G03F7/70633

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G03F7/70683

  Mark designs · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/70641

  Focus · CPC title