Selectable monolithic or external scalable die-to-die interconnection system methodology

Patent metadata

Field	Value
Publication number	US-12087689-B2
Application number	US-202318488561-A
Country	US
Kind code	B2
Filing date	Oct 17, 2023
Priority date	Sep 23, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

First claim

What is claimed is:

1. A multi-die structure including:
a routing layer including a first package-level bond pad, a second package-level bond pad, and a package-level die-to-die routing electrically connecting the first package-level bond pad to the second package-level bond pad;
a first die bonded to a first side of the routing layer and in electrical connection with the first package-level bond pad; and
a second die bonded to the first side of the routing layer and in electrical connection with the second package-level bond pad;
wherein the first die includes:
a first front-end-of-the-line (FEOL) die area including a communication device selected from the group consisting of a transceiver and a receiver; and
a first back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area, the first BEOL build-up structure including an intra-chip routing connected to the communication device, and a chip-level die-to-die routing connecting the communication device to a first bond pad of the first BEOL build-up structure, wherein the first bond pad is bonded to the routing layer and electrically connected to the first package-level bond pad.

2. The multi-die structure of claim 1 , wherein the intra-chip routing is electrically open.

3. The multi-die structure of claim 1 , wherein the first BEOL build-up structure includes a first metallic seal adjacent the first FEOL die area, wherein the intra-chip routing does is confined laterally inside the metallic seal.

4. The multi-die structure of claim 3 , wherein the first bond pad is in direct contact with the first package-level bond pad.

5. The multi-die structure of claim 4 , wherein the first die is hybrid bonded to the routing layer with dielectric-dielectric and metal-metal bonds.

6. The multi-die structure of claim 5 , wherein the routing layer includes active devices supporting logic or buffering.

7. The multi-die structure of claim 4 , wherein the routing layer is formed directly on the first die and the second die.

8. The multi-die structure of claim 7 , wherein the routing layer includes damascene interconnects.

9. The multi-die structure of claim 1 , wherein the first FEOL die area further comprises a selection device selected from the group consisting of a multiplexer and demultiplexer connected between the communication device and the chip-level die-to-die routing and the intra-chip routing.

10. The multi-die structure of claim 9 , further comprising a through silicon via connected to the selection device.

11. A multi-die structure including:
a routing layer;
a first die bonded to a first side of the routing layer and in electrical connection with the routing layer;
wherein the first die includes:
a first front-end-of-the-line (FEOL) die area including a first communication device selected from the group consisting of a transceiver and a receiver; and
a first back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area, the first BEOL build-up structure including:
a face side including a plurality of chip-level landing pads bonded to the routing layer;
a through silicon via (TSV) connecting the first communication device to a back side pad on a back side of the first die opposite the face side;

a second die bonded to the back side of the first die and in electrical communication with the back side pad.

12. The multi-die structure of claim 11 , wherein the first BEOL build-up structure includes an inter-chip routing connected to the first communication device.

13. The multi-die structure of claim 12 , wherein the second die is hybrid bonded to the first die, and the first die is hybrid bonded to the routing layer.

14. The multi-die structure of claim 12 , wherein the first FEOL die area further comprises a selection device selected from the group consisting of a multiplexer and demultiplexer connected between the first communication device and the inter-chip routing and the TSV.

15. The multi-die structure of claim 12 , wherein the first FEOL die area further comprises a second communication device and a second inter-chip routing connecting the second communication device to a bond pad that is bonded to the first side of the routing layer and in electrical connection with a third die bonded to the first side of the routing layer.

16. The multi-die structure of claim 11 , wherein the first BEOL build-up structure is a chip-level BEOL build-up structure including chip-level die-to-die routing connecting the first die to a third die formed in a same semiconductor substrate as the first die.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Zhai Jun
• Yeh Jung-Cheng
• Hu Kunzhong
• Camenforte Raymundo
• Hoffmann Thomas

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title