Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method

Patent metadata

Field	Value
Publication number	US-10515939-B2
Application number	US-201615015110-A
Country	US
Kind code	B2
Filing date	Feb 3, 2016
Priority date	Feb 17, 2015
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

First claim

What is claimed is:

1. A wafer-level package comprising:
a first die including a first set of input/output (I/O) pads having at least one I/O pad arranged on a first side of the first die;
a second die including a second set of I/O pads having at least one I/O pad arranged on a first side of the second die, wherein the second die is identical to the first die such that the first set of I/O pads arranged on the first side of the first die correspond to the second set of I/O pads arranged on the first side of the second die, respectively;
wherein the I/O pads are rotationally symmetric, such that the first set of I/O pads on the first side of the first die is configured to transmit signals to the second set of I/O pads on the first side of the second die, and a second set of I/O pads on the first side of the first die is configured to receive signals from a first set of I/O pads on the first side of the second die,
wherein the first die is arranged adjacent to the second die in a side-by-side fashion on a substrate within a plane that is parallel to a surface of the substrate such that the first side of the first die is opposed to the first side of the second die; and
a plurality of non-crossing connection paths within a single layer are configured to connect the I/O pads between the first die and the second die.

2. The wafer-level package of claim 1 , wherein the first set of I/O pads on the first side of the first die includes a first subset of I/O pads, wherein at least one I/O pad of the first subset is disposed between at least two I/O pads of at least one another subset, such that the at least one I/O pad of the first subset is disposed so as not to be directly adjacent to other I/O pads of the first subset.

3. The wafer-level package of claim 1 , wherein the second set of I/O pads on the first side of the first die includes a second subset of I/O pads, wherein at least one I/O pad of the second subset is disposed between at least two I/O pads of at least one another subset, such that the at least one I/O pad of the second subset is disposed so as not to be directly adjacent to other I/O pads of the second subset.

4. The wafer-level package of claim 1 , wherein the first set of I/O pads on the first side of the first die are arranged so as not to be directly opposite to the second set of I/O pads on the first side of the second die, and the second set of I/O pads on the first side of the first die are arranged so as not to be directly opposite to the first set of I/O pads on the first side of the second die.

5. The wafer-level package of claim 1 , wherein the first set of I/O pads on the first side of the first die are arranged so as to be directly opposite to and facing the second set of I/O pads on the first side of the second die, and the second set of I/O pads on the first side of the first die are arranged so as to be directly opposite to and facing the first set of I/O pads on the first side of the second die.

6. The wafer-level package of claim 1 , wherein the I/O pads of the first set of I/O pads are not directly adjacent to each other, and the I/O pads of the second set of I/O pads are not directly adjacent to each other.

Assignees

• Mediatek Inc

Inventors

• Chen Yi-Hung
• Liu Yuan-Chin

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/635

  Through-vias · CPC title