Interconnecting dies by stitch routing

Patent metadata

Field	Value
Publication number	US-10438896-B2
Application number	US-201715801163-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Apr 11, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

First claim

What is claimed is:

1. A stitched die structure including:
a semiconductor substrate including a first die area of a first die and a second die area of a second die separate from the first die area, wherein the first die area includes a first core logic circuit region and a first die-to-die input/output circuit region, and the second die area includes a second core logic circuit region and a second die-to-die input/output circuit region; and
a back-end-of-the-line (BEOL) build-up structure spanning over the first die area and the second die area, the BEOL build-up structure comprising a die-to-die routing to electrically connect the first die-to die input/output circuit region to the second die-to-die input/output circuit region;
wherein the die-to-die routing includes a first die routing, a second die routing, and a stitch routing physically connecting the first die routing to the second die routing.

2. The stitched die structure of claim 1 , wherein the stitch routing has a wider line width than the first die routing and the second die routing, and the stitch routing has a coarser line pitch than the first die routing and the second die routing.

3. The stitched die structure of claim 1 , wherein the first die-to-die input/output circuit region in includes a driver, and the second die-to-die input/output circuit region includes a receiver.

4. The stitched die structure of claim 3 , wherein the second die-to-die input/output circuit region comprises an antenna diode coupled to the second die-to-die routing between the receiver and the stitch routing.

5. The stitched die structure of claim 4 , wherein the first die-to-die input/output circuit region comprises a second antenna diode coupled to the first die-to-die routing between the driver and the stitch routing.

6. The stitched die structure of claim 4 , further comprising a detection circuit coupled to the receiver and a second die-to-die routing to detect presence of the first die.

7. The stitched die structure of claim 3 , further comprising a buffer enable/disable input to the driver, a first power switch input to the driver, an enable/disable input to the receiver, and a second power switch input to the receiver.

8. The stitched die structure of claim 3 , wherein the first core logic circuit region and the first die-to-die input/output circuit region are laterally separated by a first keep out zone, and the second core logic circuit region and the second die-to-die input/output circuit region are laterally separated by a second keep out zone.

9. The stitched die structure of claim 3 , wherein the BEOL build-up structure further comprises:
a first metallic seal directly over a first peripheral area of the first die area;
a second metallic seal directly over a second peripheral area of the second die area; and
the die-to-die routing extends through a first opening in the first metallic seal and a second opening in the second metallic seal to electrically connect the first die to the second die.

10. The stitched die structure of claim 9 , wherein the die-to-die routing enters the first metallic seal in a lower metal level in the BEOL build-up structure and exits the first metallic seal in an upper metal level in the BEOL build-up structure above the lower metal level.

11. The stitched die structure of claim 9 , wherein the first die area includes a third die-to-die input/output circuit region including a second receiver opposite the first core logic circuit region from the first die-to-die input/output circuit region, and the receiver is coupled with a third die routing that terminates near a diced edge of the stitched die structure.

12. The stitched die structure of claim 9 , further comprising one or more barrier layers including a substantially uniform thickness spanning along the diced edge of the stitched die structure substantially orthogonal to metal layers of the BEOL build-up structure.

13. The stitched die structure of claim 3 , further comprising a metallic seal around the first die area, the second die area, and the die-to-die routing.

14. A stitched die structure including:
a semiconductor substrate including a first die first die area of a first die and a second die area of a second die separate from the first die area;
a back-end-of-the-line (BEOL) build-up structure spanning over the first die area and the second die area, the BEOL build-up structure comprising:
a die-to-die routing electrically connecting the first die to the second die;
a metallic seal around the first die area, the second die area and the die-to die routing;
wherein the die-to-die routing includes a first die routing within the first die area, a second die routing within the second die area, and a stitch routing physically connecting the first die routing to the second die routing.

15. The stitched die structure of claim 14 , wherein the stitch routing has a wider line width than the first die routing and the second die routing, and the stitch routing has a coarser line pitch than the first die routing and the second die routing.

16. The stitched die structure of claim 14 , wherein the first die area includes a first core logic circuit region and a first die-to-die input/output circuit region, and the second die includes a second core logic circuit region and a second die-to-die input/output circuit region, and the die-to-die routing electrically connects the first die-to-die input/output circuit region to the second die-to-die input/output circuit region.

17. A stitched die structure including:
a semiconductor substrate including a first die first die area of a first die and a second die area of a second die separate from the first die area;
a back-end-of-the-line (BEOL) build-up structure spanning over the first die area and the second die area, the BEOL build-up structure comprising:
a die-to-die routing electrically connecting the first die to the second die;

a metallic seal around the first die area, the second die area and the die-to die routing;
a plurality of input/output circuits and a plurality of die input/output connections coupled to the plurality of input/output circuits with a plurality of stitch routings; and
an input/output circuit is not coupled to a die input/output connection of the die-to-die routing in the plurality of input/output circuits.

18. The stitched die structure of claim 17 , comprising a first group of the plurality of routings with a first characteristic routing pattern, and a second group of the plurality of routings with a second characteristic routing pattern, wherein a difference in the first characteristic routing pattern and the second characteristic routing pattern is correlated with the input/output circuit not being coupled to the die input/output connection.

19. A module comprising:
a module substrate;
a stitched die structure mounted on the module substrate, the stitched die structure including a first die area of a first die and a second die area of a second die, and a back-end-of-the-line (BEOL) build-up structure that spans over the first die area and the second die area and electrically connects the first die to the second die;
wherein the BEOL build-up structure comprises a die-to-die routing to electrically connect the first die-to die input/output circuit region to the second die-to-die input/output circuit region, the die-to-die routing including a first die routing, a second die routing, and a stitch routing physically connecting the first die routing to the second die routing; and
a hermetic seal surrounding the stitched d

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Zhai Zun

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/00

  Package configurations · CPC title