Single platform, multiple cycle spacer deposition and etch

Patent metadata

Field	Value
Publication number	US-9852916-B2
Application number	US-201615194456-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Jul 24, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

First claim

What is claimed is:

1. An apparatus to manufacture an electronic device, comprising:
a plurality of mask features on a device layer on a substrate, each of the plurality of mask features comprising
a top surface;
a bottom surface;
a first side surface and a second side surface between the top surface and the bottom surface;
a plurality of spacer layers between the top surface and the bottom surface, the plurality of spacer layers comprising a first spacer layer on a second spacer layer on a third spacer layer, wherein the first side surface is a part of the first spacer layer and the second side surface is a part of the third spacer layer, wherein the first side surface and the second side surface are exposed, wherein each of the spacer layers is a nitride layer.

2. The apparatus of claim 1 , wherein
the width of the plurality of spacer layers at the top surface is substantially similar to the width of the plurality of spacer layers at the bottom surface.

3. The apparatus of claim 1 , wherein the top surface is substantially parallel to the device layer.

4. The apparatus of claim 1 , wherein the bottom surface is on the device layer.

5. The apparatus of claim 1 , wherein the first side surface is substantially perpendicular to the device layer.

6. The apparatus of claim 1 , wherein the thickness of each of the spacer layers is from 5 nanometers to 10 nanometers.

7. The apparatus of claim 1 , wherein the width of the plurality of spacer layers is from 20 nanometers to 150 nanometers.

8. The apparatus of claim 1 , wherein the plurality of mask features are separated by a space that exposes a portion of the device layer.

9. The apparatus of claim 1 , wherein the top surface is at a distance away from the device layer.

10. The apparatus of claim 1 , further comprising
a device feature underneath each of the mask features.

11. An apparatus to manufacture an electronic device, comprising:
a plurality of mask features on a device layer on a substrate, each of the plurality of mask features comprising
a top surface;
a bottom surface;
a first side surface and a second side surface between the top surface and the bottom surface;

a plurality of spacer layers between the top surface and the bottom surface, the plurality of spacer layers comprising a first spacer layer on a second spacer layer on a third spacer layer, wherein the first side surface is a part of the first spacer layer and the second side surface is a part of the third spacer layer, wherein the first side surface and the second side surface are exposed, wherein the second spacer layer, the first spacer layer and the third spacer layer are of the same material.

12. An apparatus to manufacture an electronic device, comprising:
a plurality of mask features on a device layer on a substrate, each of the plurality of mask features comprising
a top surface;
a bottom surface;
a first side surface and a second side surface between the top surface and the bottom surface;

a plurality of spacer layers between the top surface and the bottom surface, the plurality of spacer layers comprising a first spacer layer on a second spacer layer on a third spacer layer, wherein the first side surface is a part of the first spacer layer and the second side surface is a part of the third spacer layer, wherein the first side surface and the second side surface are exposed, wherein the plurality of spacer layers comprise at least 5 spacer layers.

Assignees

• Applied Materials Inc

Inventors

• Chen Hao
• Ying Chentsau (Chris)
• Nemani Srinivas D
• Yieh Ellie Y

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P72/3302

  Mechanical parts of transfer devices · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P50/642

  Chemical etching · CPC title