Sidewall image transfer nanosheet

Patent metadata

Field	Value
Publication number	US-9722022-B2
Application number	US-201514979916-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

First claim

What is claimed is:

1. A method for forming active regions of a semiconductor device, the method comprising:
forming a nanosheet stack on a substrate, forming the nanosheet stack comprising:
forming a sacrificial nanosheet layer on the substrate; and
forming a nanosheet layer on the sacrificial nanosheet layer;

forming an etch stop layer on the nanosheet stack;
forming a mandrel layer on the etch stop layer;
removing portions of the mandrel layer to form a mandrel on the etch stop layer;
forming sidewalls adjacent to sidewalls of the mandrel;
depositing a fill layer on exposed portions of the etch stop layer;
removing the sidewalls; and
removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

2. The method of claim 1 , further comprising, removing the mandrel, the fill layer, and the etch stop layer.

3. The method of claim 2 , further comprising:
forming a sacrificial gate stack over the nanosheet stack; and
removing exposed portions of the sacrificial nanosheet layer of the nanosheet stack.

4. The method of claim 2 , further comprising:
forming a gate stack over the nanosheet stack; and
removing exposed portions of the sacrificial nanosheet layer of the nanosheet stack.

5. The method of claim 3 , further comprising forming a spacer adjacent to the sacrificial gate stack prior to removing the exposed portions of the sacrificial nanosheet layer.

6. The method of claim 5 , further comprising:
removing the spacer;
forming a second spacer adjacent to the sacrificial gate stack; and
forming source/drain regions on exposed portions of the nanosheet layer.

7. The method of claim 6 , further comprising:
depositing an insulator layer on the source/drain regions;
removing the sacrificial gate stack to expose a channel region of the nanosheet layer;
forming a gate stack over the exposed channel region of the nanosheet layer.

8. The method of claim 1 , wherein the forming the nanosheet stack further comprises;
forming a second sacrificial nanosheet layer on the nanosheet layer; and
forming a second nanosheet layer on the second sacrificial nanosheet layer.

9. The method of claim 1 , wherein the nanosheet layer includes a first semiconductor material and the sacrificial nanosheet layer includes a second semiconductor material.

10. The method of claim 1 , wherein the nanosheet layer includes a first epitaxially grown semiconductor material and the sacrificial nanosheet layer includes a second epitaxially grown semiconductor material.

11. The method of claim 9 , wherein the first semiconductor material is dissimilar from the second semiconductor material.

12. The method of claim 9 , wherein the first semiconductor material includes silicon and the second semiconductor material includes silicon germanium.

13. The method of claim 6 , wherein the source/drain regions include a doped epitaxially grown semiconductor material.

14. The method of claim 1 , wherein the etch stop layer includes an oxide material.

15. The method of claim 1 , wherein the etch stop layer includes a nitride material.

16. A method for a semiconductor device, the method comprising:
forming a nanosheet stack on a substrate, forming the nanosheet stack comprising:
forming a sacrificial nanosheet layer on the substrate; and
forming a nanosheet layer on the sacrificial nanosheet layer;

forming an etch stop layer on the nanosheet stack;
forming a mandrel layer on the etch stop layer;
removing portions of the mandrel layer to form a mandrel on the etch stop layer;
forming sidewalls adjacent to sidewalls of the mandrel;
depositing a fill layer on exposed portions of the etch stop layer;
removing the sidewalls;
removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate;
removing the mandrel, the fill layer, and the etch stop layer;
forming a gate stack over the nanosheet stack; and
removing exposed portions of the sacrificial nanosheet layer of the nanosheet stack.

17. The method of claim 16 , further comprising:
forming a spacer adjacent to the gate stack prior to removing the exposed portions of the sacrificial nanosheet layer;
removing the spacer after removing the exposed portions of the sacrificial nanosheet layer;
forming a second spacer adjacent to the sacrificial gate stack after removing the exposed portions of the sacrificial nanosheet layer; and
forming source/drain regions on exposed portions of the nanosheet layer.

18. The method of claim 16 , wherein the nanosheet layer includes a first semiconductor material and the sacrificial nanosheet layer includes a second semiconductor material and the first semiconductor material is dissimilar from the second semiconductor material.

19. The method of claim 16 , wherein the nanosheet layer includes a first epitaxially grown semiconductor material and the sacrificial nanosheet layer includes a second epitaxially grown semiconductor material.

Assignees

• IBM

Inventors

• Leobandung Effendi
• Yamashita Tenko

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H01L29/785

  Electricity · mapped topic