Nanosheet isolation for bulk CMOS non-planar devices

Patent metadata

Field	Value
Publication number	US-9871099-B2
Application number	US-201514936215-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Nov 9, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate including a first device region and a second device region, wherein first trench isolation structures surround said first and second device regions and extend below first and second pedestal portions of said semiconductor substrate;
a first semiconductor material fin stack located above said first pedestal portion of said semiconductor substrate;
a second semiconductor material fin stack located above said second pedestal portion of said semiconductor substrate; and
second trench isolation structures located at ends of each first semiconductor material fin stack and said second semiconductor material fin stack, wherein a portion of one of said second trench isolation structures is located directly between a bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and another of said second trench isolation structures is located directly between a bottommost surface of said second semiconductor material fin stack and said second pedestal portion of said semiconductor substrate, and wherein said portion of said one of said second trench isolation structures that is located directly between said bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and said portion of said another of said second trench isolation structures directly between said bottommost surface of said second semiconductor material fin stack contacts a sidewall surface of one of said first trench isolation structures.

2. The semiconductor structure of claim 1 , wherein an isolation spacer is located on upper portion of sidewall surfaces of said first trench isolation structure and surrounding an upper portion of said second trench isolation structure.

3. The semiconductor structure of claim 1 , wherein a topmost surface of said first and second semiconductor material fin stacks is coplanar with a topmost surface of said first trench isolation structure.

4. The semiconductor structure of claim 3 , wherein each of said first and second semiconductor material fin stacks comprises from bottom to top, alternating layers of silicon and a silicon germanium alloy, wherein each layer of silicon germanium alloy is sandwiched by a lower layer of silicon and an upper layer of silicon.

5. The semiconductor structure of claim 1 , wherein said first trench isolation structure has depth that is greater than a depth of said second trench isolation structure.

6. The semiconductor structure of claim 1 , further comprising at least one functional gate structure straddling over at least one of said first and second semiconductor material fin stacks.

7. The semiconductor structure of claim 6 , wherein a portion of said at least one functional gate structure is located between a neighboring pair of first trench isolation structures, and another portion of said at least one functional gate structure is located above said neighboring pair of first trench isolation structures.

8. The semiconductor structure of claim 1 , wherein said semiconductor substrate is a bulk semiconductor substrate.

9. The semiconductor structure of claim 1 , further comprising a first functional gate structure straddling over a portion of said first semiconductor fin stack, and a second functional gate structure straddling over another portion of said first semiconductor fin stack and a portion of said second semiconductor fin stack.

10. A method of forming a semiconductor structure, said method comprising:
providing a first semiconductor nanowire material stack located in a first device region of a semiconductor substrate and a second semiconductor nanowire material stack located in a second device region of the semiconductor substrate, wherein said first semiconductor nanowire material stack is located on a first sacrificial silicon germanium alloy portion and said second semiconductor nanowire material stack is located on a second sacrificial silicon germanium alloy portion and wherein a first trench isolation structure surrounds each of said first and second semiconductor nanowire material stacks;
forming an isolation spacer along an upper portion of each first trench isolation structure;
removing an entirety of said first and second sacrificial silicon germanium alloy portions to provide an opening within said first and second device regions, each opening having a portion directly beneath said first and second semiconductor nanowire material stacks; and
forming a second trench isolation structure within each opening, wherein a portion of said second trench isolation structure with each opening extends directly beneath said first and second semiconductor nanowire material stacks.

11. The method of claim 10 , further comprising:
forming a first semiconductor fin stack from said first semiconductor nanowire stack and a second semiconductor fin stack from said second semiconductor nanowire stack.

12. The method of claim 11 , further comprising:
forming a first functional gate structure straddling over a portion of said first semiconductor fin stack, and
forming a second functional gate structure straddling over another portion of said first semiconductor fin stack and a portion of said second semiconductor fin stack.

13. The method of claim 12 , wherein a portion of said first functional gate structure and second functional gate structure is located between a portion of a neighboring pair of said first trench isolation structures.

14. The method of claim 10 , wherein each of said first and second semiconductor nanowire structures comprises from bottom to top, alternating layers of silicon and a silicon germanium alloy, wherein each layer of silicon germanium alloy is sandwiched by a lower layer of silicon and an upper layer of silicon.

15. The method of claim 10 , wherein said forming said isolation spacer comprises:
forming a sacrificial trench isolation structure having a second depth between a neighboring pair of first trench isolation structures in said first and second device regions; and
etching through a portion of said sacrificial trench isolation structures.

16. The method of claim 10 , wherein said first and second sacrificial silicon germanium alloy portions are located on a pedestal portion of said semiconductor substrate.

17. The method of claim 16 , wherein a portion of each first trench isolation structure extends into a portion of said semiconductor substrate.

18. The method of claim 10 , wherein said removing said entirety of said first and second sacrificial silicon germanium alloy portions comprises an etching process that is selective in removing a silicon germanium alloy.

19. The method of claim 10 , wherein each first trench isolation structure has a topmost surface that is coplanar with a topmost surface of each second trench isolation structure and a topmost surface of said first and second semiconductor nanowire stack structures.

Assignees

• IBM

Inventors

• Pranatharthiharan Balasubramanian
• Ok Injo
• Seo Soon-Cheon
• Surisetty Charan Veera Venkata Satya

Classifications

• H10P50/642

  Chemical etching · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/0649 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic