Asymmetrical vertical transistor

Patent metadata

Field	Value
Publication number	US-9837403-B1
Application number	US-201615276999-A
Country	US
Kind code	B1
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.

First claim

What is claimed is:

1. A method of fabricating asymmetric vertical field effect transistors (VFETs), the method comprising:
forming mandrels above a substrate comprising a first semiconductor material;
forming a first set of spacers adjacent to each side of the mandrels;
forming trenches in portions of the substrate that are not directly below one of the mandrels or one of the first set of spacers;
filling the trenches with a second semiconductor material that is different from the first semiconductor material;
forming a second set of spacers adjacent to each respective one of the first set of spacers, wherein the second set of spacers is above the second semiconductor;
forming a plurality of fins such that each one of the plurality of fins includes a portion of the substrate below one of the first set of spacers and a portion of the second semiconductor below one of the second set of spacers adjacent to the one of the first set of spacers, wherein the forming the plurality of fins includes leaving a base layer of the substrate below the plurality of fins; and
forming gates, wherein each gate is between an adjacent pair of fins.

2. The method according to claim 1 , further comprising forming a first terminal region within the base layer of the substrate below the plurality of fins, wherein the first terminal region is a source region or a drain region.

3. The method according to claim 2 , further comprising removing the first set of spacers and the second set of spacers after forming the plurality of fins.

4. The method according to claim 3 , further comprising forming a respective second terminal region above each of the plurality of fins at an end of the fins that is farthest from the first terminal region, wherein the second terminal region is the drain region based on the first terminal region being the source region, and the second terminal region is the source region based on the first terminal region being the drain region.

5. The method according to claim 3 , further comprising forming a hardmask layer on the substrate, wherein the forming the mandrels is on the hardmask layer.

6. The method according to claim 5 , further comprising removing the hardmask layer with the first set of spacers and the second set of spacers.

7. The method according to claim 2 , further comprising forming bottom spacers above the first terminal region prior to forming the gates.

8. The method according to claim 7 , wherein the forming the bottom spacers includes forming each of the bottom spacers below a respective one of the gates.

9. The method according to claim 7 , wherein the forming the bottom spacers includes depositing at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride, silicon boron carbon nitride (SiBCN), silicon oxygen carbon nitride (SiOCN), silicon oxygen carbon (SiOC), or silicon carbon nitride (SiCN).

10. The method according to claim 1 , further comprising forming a top spacer above each of the gates.

11. The method according to claim 10 , wherein the forming the top spacer includes a directional deposition of a dielectric material.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H01L27/088 Primary

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic