Multi version library cell handling and integrated circuit structures fabricated therefrom

Patent metadata

Field	Value
Publication number	US-12067338-B2
Application number	US-202217585101-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Sep 20, 2017
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

First claim

What is claimed is:

1. A method of fabricating a layout for an integrated circuit structure, the method comprising:
designating alternating ones of a plurality of gate lines parallel along a first direction as even (E) or odd (O) along a second direction;
selecting a location for a cell type over the plurality of gate lines;
selecting between a first version of the cell type and a second version of the cell type depending on the location, the second version structurally different than the first version, wherein the selected version of the cell type has an even (E) or odd (O) designation for interconnects at edges of the cell type along the second direction, and wherein the designation of the edges of the cell type match with the designation of individual ones of the plurality of gate lines below the interconnects.

2. The method of claim 1 , wherein the interconnects have a pitch along the second direction less than a pitch of the gate lines along the second direction.

3. The method of claim 1 , wherein individual ones of the interconnects of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.

4. The method of claim 3 , wherein individual ones of the interconnects of the second version of the cell type do not align with individual ones of the plurality of gate lines along the first direction at both edges of the second version of the cell type along the second direction.

5. The method of claim 4 , wherein the cell type is an inverter cell.

6. The method of claim 1 , wherein individual ones of the interconnects of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at a first edge but not at a second edge of the first version of the cell type along the second direction.

7. The method of claim 6 , wherein individual ones of the interconnects of the second version of the cell type align with individual ones of the plurality of gate lines along the first direction at a second edge but not at a first edge of the second version of the cell type along the second direction.

8. The method of claim 7 , wherein the cell type is a NAND cell.

Assignees

• Intel Corp

Inventors

• Kumar Ranjith
• Shi Quan
• Bohr Mark T
• Yeoh Andrew W
• Chakravarty Sourav
• Chappell Barbara A
• Webb M Clair

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D84/853

  comprising FinFETs · CPC title