Cell library and data for designs

Patent metadata

Field	Value
Publication number	US-2017039312-A1
Application number	US-201615222438-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	Aug 7, 2015
Publication date	Feb 9, 2017
Grant date	—

Abstract

A cell library readable by a computer device includes cell data of a power supply reinforcement cell, specifying a conductive path that connects high-potential power supply routings located on both sides of one low-potential power supply routing with the routing interposed therebetween or low-potential power supply routings located on both sides of one high-potential power supply routing with the routing interposed therebetween, in data of plural cells which is used in designs of a semiconductor device including plural high-potential power supply routings, connected to a high-potential power supply trunk, which are separated from each other and are placed in parallel with each other, plural low-potential power supply routings, connected to a low-potential power supply trunk, which are placed alternately and in parallel with the high-potential power supply routings, and functional circuits which are formed in regions located between the high-potential power supply routings and the low-potential power supply routings.

First claim

What is claimed is:

1 . A computer program product comprising a non-transitory computer-readable storage medium containing code which, when executed by one or more processors, performs an operation for generating a design of a semiconductor device,
the computer-readable storage medium comprising a cell library comprising cell data defining a plurality of predefined cells, wherein the design of the semiconductor device comprises, in a semiconductor substrate:
a plurality of high-potential power supply routings connected to a high-potential power supply trunk, the plurality of high-potential power supply routings separated from each other and placed in parallel with each other;
a plurality of low-potential power supply routings connected to a low-potential power supply trunk, the plurality of low-potential power supply routings placed alternately and in parallel with the plurality of high-potential power supply routings; and
one or more functional circuits formed in regions located between the high-potential power supply routings and the low-potential power supply routings,
wherein the cell library comprises cell data for a power supply reinforcement cell, the power supply reinforcement cell specifying a conductive path that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings, and wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent first power supply routings.

2 . The computer program product according to claim 1 , wherein the power supply reinforcement cell has a predetermined width and a predetermined height that is twice a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view.

3 . The computer program product according to claim 2 , wherein the power supply reinforcement cell specifies:
a first power-feeding region which is provided in a first well of a first conductivity type, a first via that leads from the first power-feeding region through connection to a power supply routing of any one polarity within the low-potential power supply routing or the high-potential power supply routing to an upper routing layer thereof, a second power-feeding region which is provided in a second well of a first conductivity type formed with a well of a second conductivity type next to the first well interposed therebetween, a second via that leads from the second power-feeding region through connection to a separate power supply routing of the one polarity to an upper routing layer thereof, and a power supply reinforcement routing of the one polarity which connects the first via and the second via.

4 . The computer program product according to claim 3 , wherein the first conductivity type is an N-type, the second conductivity type is a P-type, and the power supply routing of the one polarity is a high-potential power supply routing.

5 . The computer program product according to claim 3 , wherein the first conductivity type is a P-type, the second conductivity type is an N-type, and the power supply routing of the one polarity is a low-potential power supply routing.

6 . The computer program product according to claim 2 , wherein the power supply reinforcement cell specifies:
a first via, connected to a power supply routing of any one polarity within a low-potential power supply routing or a high-potential power supply routing, which leads to an upper routing layer thereof, a second via, connected to a neighboring power supply routing of the same polarity as that of the power supply routing having the first via connected thereto, which leads to an upper routing layer thereof, and a power supply reinforcement routing of the one polarity which connects the first via and the second via.

7 . The computer program product according to claim 6 , wherein the first conductivity type is an N-type, the second conductivity type is a P-type, and the power supply routing of the one polarity is a high-potential power supply routing.

8 . The computer program product according to claim 6 , wherein the first conductivity type is a P-type, the second conductivity type is an N-type, and the power supply routing of the one polarity is a low-potential power supply routing.

9 . The computer program product according to claim 1 , wherein the power supply reinforcement cell has a predetermined width and a predetermined height that is a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view,
wherein two power supply reinforcement cells are arranged with line-symmetric placement and defined as one set, wherein the set specifies a conductive path that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings, wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent power supply routings.

10 . The computer program product according to claim 9 , wherein the power supply reinforcement cell specifies:
a first power-feeding region which is provided in a first well of a first conductivity type, a first via that leads from the first power-feeding region through connection to a power supply routing of any one polarity within the low-potential power supply routing or the high-potential power supply routing to an upper routing layer thereof, and a power supply reinforcement routing of the one polarity which is connected to the first via.

11 . The computer program product according to claim 10 , wherein the first conductivity type is an N-type, and the power supply routing of the one polarity is a high-potential power supply routing.

12 . The computer program product according to claim 10 , wherein the first conductivity type is a P-type, and the power supply routing of the one polarity is a low-potential power supply routing.

13 . The computer program product according to claim 9 , wherein the power supply reinforcement cell specifies:
a first via, connected to a power supply routing of any one polarity within a low-potential power supply routing or a high-potential power supply routing, which leads to an upper routing layer thereof, and a power supply reinforcement routing of the one polarity which is connected to the first via.

14 . The computer program product according to claim 13 , wherein the first conductivity type is an N-type, and the power supply routing of the one polarity is a high-potential power supply routing.

15 . The computer program product according to claim 13 , wherein the first conductivity type is a P-type, and the power supply routing of the one polarity is a low-potential power supply routing.

16 . A computer program product comprising a non-transitory computer-readable storage medium containing code which, when executed by one or more processors, performs an operation for generating a design of a semiconductor device, wherein the design of a semiconductor device comprises, in a semiconductor substrate:
a plurality of high-potential power supply routings connected to a high-potential power supply trunk, the plurality of high-potential power supply routings separated from each other and placed in parallel with each other; a plurality of low-potential power supply routings connected to a low-potential p

Assignees

• Synaptics Japan Gk

Inventors

• Fukaya Tomohiro

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2111/06

  Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title