Internal node jumper for memory bit cells

Patent metadata

Field	Value
Publication number	US-11205616-B2
Application number	US-201716604807-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Jun 20, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a memory bit cell on a substrate, the memory bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate;
first and second gate lines over the first, second, third and fourth active regions, the first and second gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction of the substrate, wherein the first and second interconnect lines are electrically connected to the first and second gate lines at locations of the first and second gate lines over one or more of the first, second, third and fourth active regions, wherein the third interconnect line electrically couples together a pair of gate electrodes of the memory bit cell or electrically couples together a pair of trench contacts of the memory bit cell, and wherein one of the first, second or third interconnect lines is vertically over and in alignment with one of the first or second gate lines.

2. The integrated circuit structure of claim 1 , wherein the third interconnect line electrically couples together the pair of gate electrodes of the memory bit cell.

3. The integrated circuit structure of claim 1 , wherein the third interconnect line electrically couples together the pair of trench contacts of the memory bit cell.

4. The integrated circuit structure of claim 1 , wherein the first active region is a P-type doped active region, the second active region is an N-type doped active region, the third active region is an N-type doped active region, and the fourth active region is an N-type doped active region.

5. The integrated circuit structure of claim 1 , wherein the first, second, third and fourth active regions are in silicon fins.

6. The integrated circuit structure of claim 1 , wherein the memory bit cell comprises a pull-up transistor based on a single silicon fin, a pass-gate transistor based on two silicon fins, and a pull-down transistor based on two silicon fins.

7. The integrated circuit structure of claim 1 , wherein the first and second gate lines alternate with individual ones of a plurality of trench contact lines parallel along the second direction of the substrate, the plurality of trench contact lines comprising the pair of trench contacts of the memory bit cell.

8. The integrated circuit structure of claim 1 , wherein the first and second gate lines have a first pitch along the first direction, the first, second and third interconnect lines have a second pitch along the first direction, and wherein the second pitch is less than the first pitch.

9. The integrated circuit structure of claim 1 , wherein the first pitch is in the range of 50 nanometers to 60 nanometers, and wherein the second pitch is in the range of 30 nanometers to 40 nanometers.

10. The integrated circuit structure of claim 1 , wherein the first and second interconnect lines are electrically connected to the first and second gate lines by an intervening plurality of interconnect lines between the first and second interconnect lines and the first and second gate lines, and wherein the intervening plurality of interconnect lines is parallel along the first direction of the substrate.

11. An integrated circuit structure, comprising:
a memory bit cell on a substrate, the memory bit cell comprising:
first and second gate lines parallel along a second direction of the substrate, wherein the first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction of the substrate, wherein the first, second and third interconnect lines have a second pitch along the first direction, wherein the second pitch is less than the first pitch, wherein one of the first, second and third interconnect lines is an internal node jumper for the memory bit cell, and wherein one of the first, second or third interconnect lines is vertically over and in alignment with one of the first or second gate lines.

12. The integrated circuit structure of claim 11 , wherein the internal node jumper electrically couples together a pair of gate electrodes of the memory bit cell.

13. The integrated circuit structure of claim 11 , wherein the internal node jumper electrically couples together a pair of trench contacts of the memory bit cell.

14. The integrated circuit structure of claim 11 , wherein the first and second gate lines alternate with individual ones of a plurality of trench contact lines parallel along the second direction of the substrate.

15. The integrated circuit structure of claim 11 , wherein the first pitch is in the range of 50 nanometers to 60 nanometers, and wherein the second pitch is in the range of 30 nanometers to 40 nanometers.

16. An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate, wherein the first active region comprises two silicon fins, the second active region comprises one silicon fin, the third active region comprises one silicon fin, and the fourth active region comprises two silicon fins;
first and second gate lines over the first and second active regions, the first and second gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction of the substrate, wherein one of the first, second or third interconnect lines is vertically over and in alignment with one of the first or second gate lines.

17. The integrated circuit structure of claim 16 , wherein the first and fourth active regions are P-type doped active regions, and the second and third active regions are N-type doped active regions.

18. The integrated circuit structure of claim 16 , wherein individual ones of the first and second gate lines are spaced apart from one another by trench contact lines parallel along the second direction of the substrate.

19. The integrated circuit structure of claim 16 , wherein contact to the first and second gate lines is made to active gate locations of the first and second gate lines.

20. The integrated circuit structure of claim 16 , wherein 6T SRAM bit cell comprises an internal node jumper.

21. An integrated circuit structure, comprising:
a fin comprising silicon;
a first gate electrode and a second gate electrode over the fin, the first and second gate electrodes along a first direction, and the first and second gate electrodes having a first pitch;
a first plurality of metal lines above the first and second gate electrodes;
a gate contact coupling one of the first plurality of metal lines to the first gate electrode at a location vertically over the fin;
a second plurality of metal lines over the first plurality of metal lines, wherein metal lines of the second plurality of metal lines are along the first direction and hav

Assignees

• Intel Corp

Inventors

• Shridharan Smita
• Guo Zheng
• Karl Eric A
• Shchupak George
• Kosinovsky Tali

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title