Densely packed standard cells for integrated circuit products, and methods of making same
US-8975712-B2 · Mar 10, 2015 · US
Semiconductor device
US2017194329A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017194329-A1 |
| Application number | US-201615205421-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 8, 2016 |
| Priority date | Jan 4, 2016 |
| Publication date | Jul 6, 2017 |
| Grant date | — |
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Abstract
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A cell includes a plurality of fin transistors formed in a semiconductor substrate. In the cell, a fin serving as a source and drain of each of the plurality of fin transistors is arranged in plurality at a first pitch in a first direction. Moreover, the cell height that is the length in the first direction of the cell is an n multiple (n is an integer) of half the length of the first pitch. Wires are connected to the cell, and are arranged at a second pitch, which is a 1/m multiple (m is an integer) of the cell height in the first direction.
First claim
Opening claim text (preview).
1 . A semiconductor device comprising: a semiconductor substrate; a cell including a plurality of fin transistors formed in the semiconductor substrate, wherein a fin serving as a source and drain of each of the plurality of fin transistors is arranged in plurality at a first pitch in a first direction and a cell height of the cell that is a length in the first direction is an odd number multiple of half a length of the first pitch; and a plurality of wires connected to the cell and arranged at a second pitch that is a 1/m multiple (m is an integer) of the cell height in the first direction. 2 . The semiconductor device according to claim 1 , wherein the cell is a standard cell, wherein the standard cell is arranged in plurality in a plurality of areas provided by partitioning the 20 semiconductor substrate, the plurality of areas having the cell height in the first direction, and wherein a first standard cell arranged in a first area among the plurality of areas is reversely arranged in the first direction with respect to a second standard cell, which is arranged in a second area adjacent to the first area, so as to share one of a power supply line and a ground line with the second standard cell. 3 .- 9 . (canceled) 10 . A semiconductor device comprising: a semiconductor substrate; and a cell including a plurality of fin transistors formed in the semiconductor substrate, wherein a fin serving as a source and drain of each of the plurality of fin transistors is arranged in plurality at a first pitch in a first direction and a cell height of the cell that is a length in the first direction is an odd number multiple of half a length of the first pitch.
Assignees
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Classifications
Power or ground buses · CPC title
comprising FinFETs · CPC title
Electricity · mapped topic
Electricity · mapped topic
- H01L27/1104Primary
Electricity · mapped topic
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- What does patent US2017194329A1 cover?
- A cell includes a plurality of fin transistors formed in a semiconductor substrate. In the cell, a fin serving as a source and drain of each of the plurality of fin transistors is arranged in plurality at a first pitch in a first direction. Moreover, the cell height that is the length in the first direction of the cell is an n multiple (n is an integer) of half the length of the first pitch. Wi…
- Who is the assignee on this patent?
- Socionext Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L27/1104. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).