Method and system of forming layout design

Patent metadata

Field	Value
Publication number	US-9626472-B2
Application number	US-201414555175-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

First claim

What is claimed is:

1. A method of forming a layout design for fabricating an integrated circuit, the method comprising:
placing a first set of layout patterns in a first layout layer, the first set of layout patterns being aligned with one or more grid lines of a first set of grid lines, the first set of layout patterns corresponding to fabricating a first set of components in a first component layer of the integrated circuit, the first set of grid lines extending along a first direction, a first grid line of the first set of grid lines overlapping a first cell boundary of a standard cell layout, and a second grid line of the first set of grid lines overlapping a second cell boundary of the standard cell layout; and
placing a second set of layout patterns in a second layout layer, the second set of layout patterns being aligned with one or more grid lines of a second set of grid lines, the second set of layout patterns corresponding to fabricating a second set of components in a second component layer of the integrated circuit, the second set of grid lines extending along the first direction and having at least two different line pitches, a first grid line of the second set of grid lines overlapping the first cell boundary of the standard cell layout, and a second grid line of the second set of grid lines overlapping the second cell boundary of the standard cell layout, and
at least one of the above operations being performed by a hardware processor.

2. The method of claim 1 , further comprising:
generating the first set of layout patterns, each layout pattern of the first set of layout patterns having a first width.

3. The method of claim 2 , further comprising:
generating the second set of layout patterns, each layout pattern of the second set of layout patterns having a second width.

4. The method of claim 1 , further comprising:
generating the second set of layout patterns, the second set of layout patterns comprising:
a first layout pattern having a first width; and
a second layout pattern having a second width different from the first width, the first layout pattern and the second layout pattern of the second set of layout patterns being aligned with different grid lines of the second set of grid lines.

5. The method of claim 1 , further comprising:
generating the second set of layout patterns, the second set of layout patterns comprising:
a first layout pattern having a first width;
a second layout pattern having a second width; and
a third layout pattern having a third width,
wherein
the first layout pattern, the second layout pattern, and the third layout pattern of the second set of layout patterns are aligned with different grid lines of the second set of grid lines; and
the first width, the second width, and the third width are different.

6. The method of claim 1 , further comprising:
generating the second set of layout patterns, the second set of layout patterns comprising:
a first layout pattern aligned with the first grid line of the second set of grid lines and having a first width; and
a second layout pattern aligned with the second grid line of the second set of grid lines and having a second width different from the first width.

7. The method of claim 1 , wherein the first component layer and the second component layer are independently chosen from the following component layers of the integrated circuit:
a fin structure layer for FinFETs;
a first conductive layer over the fin structure layer; and
a second conductive layer over the first conductive layer.

8. The method of claim 1 , wherein the first component layer and the second component layer are independently chosen from the following component layers of the integrated circuit:
a gate structure layer;
a first conductive layer over the gate structure layer; and
a second conductive layer over the first conductive layer.

9. The method of claim 1 , further comprising:
placing a third set of layout patterns in a third layout layer, the third set of layout patterns extending along a second direction and being aligned with a third cell boundary and a fourth cell boundary of the standard cell layout, the third set of layout patterns corresponding to a portion of the second set of components that is configured to be removed by a removal process.

10. A system of forming a layout design, comprising:
a non-transitory storage medium encoded with a set of instructions;
a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instruction, the set of instruction being configured to cause the processor to:
place a first set of layout patterns in a first layout layer, the first set of layout patterns being aligned with one or more grid lines of a first set of grid lines, the first set of layout patterns corresponding to fabricating a first set of components in a first component layer of an integrated circuit, the first set of grid lines extending along a first direction, a first grid line of the first set of grid lines overlapping a first cell boundary of a standard cell layout, and a second grid line of the first set of grid lines overlapping a second cell boundary of the standard cell layout; and
place a second set of layout patterns in a second layout layer, the second set of layout patterns being aligned with one or more grid lines of a second set of grid lines, the second set of layout patterns corresponding to fabricating a second set of components in a second component layer of the integrated circuit, the second set of grid lines extending along the first direction and having at least two different line pitches, a first grid line of the second set of grid lines overlapping the first cell boundary of the standard cell layout, and a second grid line of the second set of grid lines overlapping the second cell boundary of the standard cell layout.

11. The layout designing system of claim 10 , wherein the set of instruction is configured to cause the processor to:
generate the first set of layout patterns, each layout pattern of the first set of layout patterns having a first width.

12. The layout designing system of claim 11 , wherein the set of instruction is configured to cause the processor to:
generate the second set of layout patterns, each layout pattern of the second set of layout patterns having a second width.

13. The layout designing system of claim 10 , wherein the set of instruction is configured to cause the processor to:
generate the second set of layout patterns, the second set of layout patterns comprising:
a first layout pattern having a first width; and
a second layout pattern having a second width different from the first width, the first layout pattern and the second layout pattern of the second set of layout patterns being aligned with different grid lines of the second set of grid lines.

14. The layout designing system of claim 10 , wherein the set of instruction is configured to cause the processor to:
generate the second set of layout patterns, the second set of layout patterns comprising:
a first layout pattern having a first width;
a second layout pattern having a second width; and
a third layout pattern having a third width,
wherein
the first layout pattern, the second layout pattern, and the third layout pattern of the second set of layout patterns are aligned with different grid lines of the second set of grid lines; and
the first width, the second width, and the third width are different.

15. The layout designing system of claim 10 , wherein the set of instruction is configured to cause the processor t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Ting-Wei
• Tien Li-Chun
• Zhuang hui-zhong
• Jiang Zhe-Wei

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L27/0886

  Electricity · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic