Selectively roughened copper architectures for low insertion loss conductive features

Patent metadata

Field	Value
Publication number	US-12033930-B2
Application number	US-202017033392-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

First claim

We claim:

1. An integrated circuit (IC) package substrate, comprising:
a metallization level within a dielectric material, wherein the metallization level comprises a plurality of conductive features each having a top surface and a sidewall surface,
wherein the top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness,
wherein the sidewall surface of the first conductive feature has a third average surface roughness that is greater than the second average surface roughness and the top surface of the second conductive feature has a fourth average surface roughness that is less than the first average surface roughness,
wherein the second conductive feature comprises a first material, and wherein a second material is over the top surface and the sidewall surface of the second conductive feature.

2. The IC package substrate of claim 1 , wherein the second material comprises any one of gold, silver, aluminum, nickel, tungsten, cobalt, molybdenum, titanium, carbon, hydrogen, silicon, nitrogen, fluorine, chlorine, or oxygen.

3. The IC package substrate of claim 1 , wherein the second material comprises atoms of sulfur and carbon, wherein the atoms of sulfur are covalently bound to the first material, and wherein the atoms of carbon are within an n-hydrocarbon chain comprising at least two atoms of carbon and terminating at an atom of nitrogen, wherein the n-hydrocarbon chain is within a self-assembled monolayer over the top surface and the sidewall surface of the second conductive feature.

4. The IC package substrate of claim 3 , wherein the first material comprises copper or an alloy of copper.

5. The IC package substrate of claim 1 , wherein the first conductive feature is physically coupled to a via.

6. The IC package substrate of claim 5 , wherein the first conductive feature comprises a pad and the via extends over or under the pad.

7. The IC package substrate of claim 1 , wherein the first average surface roughness is not less than twice the second average surface roughness.

8. An integrated circuit (IC) package substrate, comprising:
a metallization level within a dielectric material, wherein the metallization level comprises a plurality of conductive features each having a top surface and a sidewall surface,
wherein the top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness,
wherein the sidewall surface of the first conductive feature has a third average surface roughness that is greater than the second average surface roughness and the top surface of the second conductive feature has a fourth average surface roughness that is less than the first average surface roughness, and
wherein the top surface and the sidewall surface of the second conductive feature are substantially curved.

9. The IC package substrate of claim 8 , wherein the first conductive feature and the second conductive feature each comprise copper or an alloy of copper.

10. The IC package substrate of claim 8 , wherein the second conductive feature comprises an ovoid profile.

11. The IC package substrate of claim 8 , wherein the first conductive feature is physically coupled to a via.

12. The IC package substrate of claim 11 , wherein the first conductive feature comprises a pad and the via extends over or under the pad.

13. The IC package substrate of claim 8 , wherein the first average surface roughness is not less than twice the second average surface roughness.

14. An integrated circuit (IC) package substrate, comprising: a metallization level within a dielectric material, wherein the metallization level comprises a plurality of conductive features each having a top surface and a sidewall surface, wherein the top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness and the sidewall surface of the first conductive feature has a second average surface roughness, wherein the top surface of a second conductive feature of the plurality of conductive features has a third average surface roughness and the sidewall surface of the second conductive feature has a fourth average roughness, wherein the fourth average roughness is less than each of the first, second, and third average roughnesses, wherein an entirety of the top surface of the first conductive feature is roughened, wherein an entirety of the sidewall surface of the first conductive feature is roughened, wherein an entirety of the top surface of the second conductive feature is roughened and an entirety of the sidewall surface of the second conductive feature is smooth.

15. The IC package substrate of claim 14 , wherein the first conductive feature and the second conductive feature each comprise copper or an alloy of copper.

16. The IC package substrate of claim 14 , wherein the first conductive feature is physically coupled to a via.

17. The IC package substrate of claim 16 , wherein the first conductive feature comprises a pad and the via extends over or under the pad.

18. The IC package substrate of claim 14 , wherein the first, second, and third average roughnesses are each not less than twice the fourth average surface roughness.

Assignees

• Intel Corp

Inventors

• Kong Jieying
• Zhou Yiyang
• Nad Suddhasattwa
• Ecton Jeremy
• Feng Hongxia
• Ibrahim Tarek
• Marin Brandon
• Qian Zhiguo
• Blythe Sarah
• Shan Bohan
• Steill Jason
• Chavali Sri Chaitra Jyotsna
• Arana Leonel
• Xu Dingying
• Wall Marcel

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/092

  Adapting interconnections, e.g. making engineering charges, repairing · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title