High-speed interconnects for printed circuit boards

Patent metadata

Field	Value
Publication number	US-10051746-B2
Application number	US-201514970479-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 16, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.

First claim

What is claimed is:

1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer;
reinforcing filling material within one or each of the first insulating layer and second insulating layer; and
a conductive interconnect comprising a first surface adjacent to the first insulating layer and a second surface opposite the first surface and adjacent to the second insulating layer, wherein at least a first region of the first surface exhibits greater adhesion to the first insulating layer than a second region of the first surface.

2. The printed circuit board of claim 1 , wherein the first region includes a chemical adhesion promoter.

3. The printed circuit board of claim 1 , wherein the first region includes one or more material depositions between the conductive interconnect and the first insulating layer that provide a greater adhesion than the conductive interconnect to a cured form of the first insulating layer.

4. The printed circuit board of claim 1 , wherein the first region has a first surface roughness greater than a second surface roughness of the second region.

5. The printed circuit board of claim 4 , wherein the conductive interconnect is formed from a rolled or rolled annealed metallic foil.

6. The printed circuit board of claim 5 , wherein the metallic foil comprises copper.

7. The printed circuit board of claim 4 , wherein the second region extends across a trace of the conductive interconnect and the first region extends across a pad attached to the trace, and wherein a transition between the first region and the second region occurs at a junction between the trace and the pad of the conductive interconnect.

8. The printed circuit board of claim 7 , wherein the transition between the first region and the second region occurs within 2 mm of the junction.

9. The printed circuit board of claim 7 , wherein the pad comprises a conductive area having a width greater than a width of the trace and having a hole in the conductive area.

10. The printed circuit board of claim 4 , wherein the first surface roughness is an average peak-to-peak value measured over the first region and the second surface roughness is an average peak-to-peak value measured over the second region.

11. The printed circuit board of claim 10 , wherein the first region has a lateral dimension between 0.25 mm and 1.0 mm and the second region has a lateral dimension between 100 microns and 300 microns, and the first surface roughness is at least 25% greater than the second surface roughness.

12. The printed circuit board of claim 4 , further comprising a conductive reference plane having a third surface adjacent the first insulating layer, wherein the third surface has a third roughness approximately equal to the first surface roughness.

13. The printed circuit board of claim 1 , wherein the conductive interconnect supports NRZ data transmission rates between 40 Gb/s and 60 Gb/s with less than 25 dB of loss.

14. The printed circuit board of claim 1 , wherein the reinforcing filling material is fibrous.

15. The printed circuit board of claim 1 , wherein one or each of the first insulating layer and second insulating layer comprises polytetrafluoroethylene, fluorinated ethylene propylene, polyimide, polyether ether ketone, epoxy, polyphenylene oxide, polyphenylene ether, cyanate ester, and hydrocarbon or a polyester.

16. The printed circuit board of claim 1 , wherein a thickness of one or each of the first insulating layer and second insulating layer is less than 200 microns.

17. A method of making a printed circuit board, the method comprising:
patterning, in a conductive film on a laminate, a plurality of conductive interconnects having a plurality of first surfaces, wherein the conductive film has an average peak-to-peak surface roughness between 0.4 micron and 1 micron over the area of a conductive interconnect;
treating at least first portions of the first surfaces to increase adhesion of the first portions to an insulating layer of the printed circuit board; and
forming a mask over second portions of the conductive interconnects, wherein the forming comprises patterning a resist to cover approximately all of circuit traces of the conductive interconnects and exposing a plurality of pads attached to the circuit traces.

18. The method of claim 17 , wherein the treating comprises applying a chemical adhesion promoter to the first portions.

19. The method of claim 17 , wherein the treating comprises forming at least one material on the first portions that increases adhesion of the first portions, compared to untreated portions, to a cured form of the insulating layer.

20. The method of claim 17 , wherein the treating comprises roughening a surface of the first portions.

21. The method of claim 20 , wherein the roughening comprises etching, oxidizing, plating, or abrading the first portions.

22. The method of claim 17 , wherein the first portions comprise circuit traces and untreated portions comprise pads.

23. The method of claim 17 , wherein the treated first portions of the conductive interconnects comprise less than 5% by length of the conductive interconnects.

24. The method of claim 17 , wherein the conductive interconnects comprise a rolled or rolled annealed metallic foil.

25. The method of claim 17 , wherein the conductive interconnects comprise copper.

26. A printed circuit board comprising:
an insulating layer;
a plurality of interconnects formed from a rolled metallic film that are adjacent to the insulating layer; and
reinforcing filling material located within the insulating layer that stiffens the printed circuit board, wherein the conductive interconnect supports NRZ data transmission rates between 40 Gb/s and 60 Gb/s with less than 25 dB of loss.

27. The printed circuit board of claim 26 , wherein the rolled metallic film comprises copper.

28. The printed circuit board of claim 26 , wherein:
each of the plurality of interconnects includes a circuit trace having a first region; and
at least some of the plurality of interconnects include a second region treated to increase adhesion to the insulating layer compared to the first region.

29. The printed circuit board of claim 28 , wherein the first region has a first surface roughness that is less than a second surface roughness of the second region.

30. The printed circuit board of claim 28 , wherein the second region includes a chemical adhesion promoter that is not present in the first region.

31. The printed circuit board of claim 28 , wherein the first region and the second region include a chemical adhesion promoter.

32. The printed circuit board of claim 28 , wherein the second region includes one or more layers that are not present in the first region and that increase adhesion of the second region to a cured form of the insulating layer.

33. The printed circuit board of claim 28 , wherein the first region and the second region include one or more layers that increase adhesion of the first region and the second region to a cured form of the insulating layer.

34. The printed circuit board of claim 26 , wherein the insulating layer comprises polytetrafluoroethylene, fluorinated ethylene propylene, polyimide, polyether ether ketone, epoxy, polyphenylene oxide, po

Assignees

• Amphenol Corp

Inventors

• Harkness Jr Arthur E
• Kenny-Mcdermott Eva M
• Farineau Paul W
• Lavallee Raymond A
• Fancher Michael

Classifications

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/0242 Primary

  Structural details of individual signal conductors, e.g. related to the skin effect · CPC title

• H05K1/0373

  containing additives, e.g. fillers (H05K1/036 takes precedence) · CPC title

• H05K3/382

  by special treatment of the metal · CPC title

• H05K3/202

  using self-supporting metal foil pattern · CPC title