Printed wiring board

US2016174372A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016174372-A1
Application numberUS-201514971309-A
CountryUS
Kind codeA1
Filing dateDec 16, 2015
Priority dateDec 16, 2014
Publication dateJun 16, 2016
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A printed wiring board includes a first insulating layer having concave portions on first surface of the first insulating layer, a first conductor layer including first circuits formed in the concave portions, a second conductor layer including second circuits on second surface of the first insulating layer, a first via conductor connecting the first and second conductor layers, and a second insulating layer formed on the second surface of the first insulating layer and covering the second conductor layer. Each first circuit has upper, lower and side surfaces such that the upper surface is exposed from the first insulating layer and the side and lower surfaces are not roughened surfaces, each second circuit has top, back and side surfaces such that the side and back surfaces are roughened surfaces, and a thinnest first circuit has a line width L 1 smaller than a line width L 2 of a thinnest second circuit.

First claim

Opening claim text (preview).

What is claimed is: 1 . A printed wiring board, comprising: a first resin insulating layer having a plurality of concave portions formed on a first surface of the first resin insulating layer; a first conductor layer comprising a plurality of first conductor circuits formed in the concave portions of the first resin insulating layer, respectively; a second conductor layer comprising a plurality of second conductor circuits formed on a second surface of the first resin insulating layer on an opposite side with respect to the first surface of the first resin insulating layer; a first via conductor formed in the first resin insulating layer such that the first via conductor is penetrating through the first resin insulating layer and connecting the first conductor layer and the second conductor layer; and a second resin insulating layer formed on the second surface of the first resin insulating layer such that the second resin insulating layer is covering the second conductor layer, wherein each of the first conductor circuits has an upper surface, a lower surface and two side surfaces between the upper surface and the lower surface such that the upper surface is exposed from the first surface of the first resin insulating layer and that the side surfaces and the lower surface are not roughened surfaces, each of the second conductor circuits has a top surface, a back surface and two side surfaces between the top surface and the back surface such that the side surfaces and the back surface are roughened surfaces, and the plurality of first conductor circuits includes a thinnest first conductor circuit such that the thinnest first conductor circuit has a line width L 1 which is smaller than a line width L 2 of a thinnest second conductor circuit of the second conductor circuits. 2 . A printed wiring board according to claim 1 , wherein the plurality of first conductor circuits is formed such that a plurality of first spaces is formed between adjacent first conductor circuits, the plurality of second conductor circuits is formed such that a plurality of second spaces is formed between adjacent second conductor circuits, and the plurality of first spaces includes a narrowest first space such that the narrowest first space has a space S 1 which is narrower than a space S 2 of a narrowest second space of the second spaces. 3 . A printed wiring board according to claim 1 , wherein the plurality of first conductor circuits is formed such that the upper surface has a roughened surface. 4 . A printed wiring board according to claim 1 , wherein the first surface of the first resin insulating layer is formed such that the first surface of the first resin insulating layer is an exposed surface and that each of the first conductor circuits has the upper surface which is an exposed surface. 5 . A printed wiring board according to claim 1 , further comprising: a third resin insulating layer formed on the first surface of the first resin insulating layer; and a third conductor layer formed on that the third resin insulating layer resin insulating layer such that the third conductor layer is protruding from a surface of the third resin insulating layer on an opposite side with respect to the first surface of the first resin insulating layer. 6 . A printed wiring board according to claim 5 , wherein the first conductor layer and the third conductor layer are formed such that the first conductor layer and the third conductor layer are not embedded into the third resin insulating layer. 7 . A printed wiring board according to claim 1 , wherein the first resin insulating layer has a mounting surface configured to mount a first electronic component and a second electronic component, and the plurality of first conductor circuits in the first conductor layer is configured to transmit data from the first electronic component to the second electronic component. 8 . A printed wiring board according to claim 5 , wherein the third resin insulating layer is formed such that the third resin insulating layer has a thickness which is greater than a thickness of the first resin insulating layer. 9 . A printed wiring board according to claim 1 , wherein the thinnest first conductor circuit of the plurality of first conductor circuits has the line width L 1 in a range of 2.5 μm to 7.5 μm. 10 . A printed wiring board according to claim 2 , wherein the thinnest first conductor circuit of the plurality of first conductor circuits has the line width L 1 in a range of 2.5 μm to 7.5 μm, and the narrowest first space of the plurality of first spaces has the space S 1 in a range of 2.5 μm to 7.5 μm. 11 . A printed wiring board according to claim 5 , wherein the third resin insulating layer has a mounting surface configured to mount a first electronic component and a second electronic component, and the plurality of first conductor circuits in the first conductor layer is configured to transmit data from the first electronic component to the second electronic component. 12 . A printed wiring board according to claim 2 , wherein the plurality of first conductor circuits is formed such that the upper surface has a roughened surface. 13 . A printed wiring board according to claim 2 , wherein the first surface of the first resin insulating layer is formed such that the first surface of the first resin insulating layer is an exposed surface and that each of the first conductor circuits has the upper surface which is an exposed surface. 14 . A printed wiring board according to claim 2 , further comprising: a third resin insulating layer formed on the first surface of the first resin insulating layer; and a third conductor layer formed on that the third resin insulating layer resin insulating layer such that the third conductor layer is protruding from a surface of the third resin insulating layer on an opposite side with respect to the first surface of the first resin insulating layer. 15 . A printed wiring board according to claim 14 , wherein the first conductor layer and the third conductor layer are formed such that the first conductor layer and the third conductor layer are not embedded into the third resin insulating layer. 16 . A printed wiring board according to claim 2 , wherein the first resin insulating layer has a mounting surface configured to mount a first electronic component and a second electronic component, and the plurality of first conductor circuits in the first conductor layer is configured to transmit data from the first electronic component to the second electronic component. 17 . A printed wiring board according to claim 14 , wherein the third resin insulating layer is formed such that the third resin insulating layer has a thickness which is greater than a thickness of the first resin insulating layer. 18 . A printed wiring board according to claim 2 , wherein the thinnest first conductor circuit of the plurality of first conductor circuits has the line width L 1 in a range of 2.5 μm to 7.5 μm. 19 . A printed wiring board according to claim 13 , wherein the thinnest first conductor circuit of the plurality of first conductor circuits has the line width L 1 in a range of 2.5 μm to 7.5 μm, and the narrowest first space of the plurality of first spaces has the space S 1 in a range of 2.5 μm to 7.5 μm. 20 . A printed wiring board according to claim 14 , wherein the third resin insulating layer has a mounting surface configured to mount a first electronic component and a second electronic component, and th

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • Bond pads specially adapted therefor · CPC title

  • Vias, e.g. via plugs · CPC title

  • comprising multiple insulating layers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2016174372A1 cover?
A printed wiring board includes a first insulating layer having concave portions on first surface of the first insulating layer, a first conductor layer including first circuits formed in the concave portions, a second conductor layer including second circuits on second surface of the first insulating layer, a first via conductor connecting the first and second conductor layers, and a second in…
Who is the assignee on this patent?
Ibiden Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/113. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).