Semiconductor package and method for making the same

Patent metadata

Field	Value
Publication number	US-12027433-B2
Application number	US-202217885401-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Dec 31, 2019
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
positioning a package lid over a chip disposed over a first main surface of a first substrate, wherein the package lid has a wall portion and a plurality of spacers extending from the wall portion, and the first substrate has a plurality of holes corresponding to the plurality of spacers and a solder material is disposed over the semiconductor chip;
positioning the spacers into the plurality of holes so that the plurality of spacers pass through, from the first main surface, the first substrate and extend beyond a second opposing main surface of the first substrate, and the solder material contacts the package lid; and
melting the solder material by applying heat through the package lid, to form a packaged semiconductor device, wherein:
a diameter of the plurality of spacers is smaller than a width of the wall portion, and
an outer surface of the wall portion is flush with an outermost portion of the plurality of spacers, or an inner surface of the wall portion is flush with an innermost portion of the plurality of spacers.

2. The method of claim 1 , wherein the package lid is made of aluminum, aluminum alloy, copper, copper alloy, stainless steel or ceramic.

3. The method of claim 1 , wherein the package lid is made of a copper alloy selected from the group consisting of CuMo, CuW, and CuBe.

4. The method of claim 1 , wherein an under-fill material is disposed between a bottom of the chip and the first main surface of a first substrate.

5. The method of claim 4 , wherein the under-fill material is disposed over side faces of the chip.

6. The method of claim 5 , wherein the under-fill material is as a silica filled epoxy resin.

7. The method of claim 1 , wherein a ball grid array is disposed over the second main surface of the first substrate.

8. The method of claim 7 , wherein the ball grid array has a pitch ranging from 200 μm to 800 μm.

9. A method of manufacturing a semiconductor package, the method comprising:
positioning a package lid over a chip disposed over a first main surface of a first substrate, wherein the package lid has a wall portion and a plurality of spacers extending from the wall portion, and the first substrate has a plurality of holes corresponding to the plurality of spacers, a solder material is disposed over the semiconductor chip and a ball grid array is disposed over a second main surface of the first substrate;
positioning the spacers into the plurality of holes so that the plurality of spacers pass through, from the first main surface, the first substrate and extend beyond the second main surface of the first substrate, and the solder material contacts the package lid;
melting the solder material by applying heat through the package lid, to form a packaged semiconductor device; and
mounting the packaged semiconductor device to a second substrate such that the ball grid array and the plurality of spacers contact the second substrate, wherein:
a diameter of the plurality of spacers is smaller than a width of the wall portion, and
an outer surface of the wall portion is flush with an outermost portion of the plurality of spacers, or an inner surface of the wall portion is flush with an innermost portion of the plurality of spacers,
heat is applied to at least partially melt solder balls of the ball grid array to bond the solder balls to electrodes disposed over the second substrate, and
the solder material is one of SnAgCu, CuSnNi, AgCuSbSn or CuSn.

10. The method of claim 9 , wherein a pressure is applied to the solder balls of the ball grid array.

11. The method of claim 10 , wherein while the pressure is applied, a variation in distance of a gap between the second main surface of the first substrate and the second substrate is 1% to 5% of an average distance of the gap.

12. The method of claim 9 , wherein an extension amount of the plurality of spacers from the second main surface is greater than a thickness of the ball grid array.

13. The method of claim 12 , wherein the second substrate includes a plurality of recesses to which the plurality of spacers are fitted.

14. The method of claim 13 , wherein an end of the plurality of spacers has a thin portion that fits a corresponding one of the plurality of recesses.

15. A method of manufacturing a semiconductor package, the method comprising:
positioning a package lid over a chip disposed over a first main surface of a first substrate, wherein the package lid has a plurality of spacers extending from a periphery of the package lid, and the first substrate has a plurality holes corresponding to the plurality of spacers; and
positioning the spacers into the holes so that the spacers pass through a first main surface of the substrate and extend beyond a second opposing main surface of the substrate, to form a packaged semiconductor device,
wherein the chip is an image sensor or a light sensor.

16. The method of claim 15 , wherein the package lid is made of aluminum, aluminum alloy, copper, copper alloy, stainless steel or ceramic.

17. The method of claim 15 , wherein the package lid in a ring or a frame shape having an opening.

18. The method of claim 17 , wherein a transparent cover is disposed over the opening.

19. The method of claim 15 , further comprising mounting the packaged semiconductor device to a second substrate.

20. The method of claim 19 , wherein heat and pressure are applied when mounting the packaged semiconductor device to the second substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yang-Che
• Lin Chen-Hua
• Tseng Huang-Wen
• Liang Victor Chiang
• Liu Chwen-Ming

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title