Methods and apparatus for wafer level packaging

Patent metadata

Field	Value
Publication number	US-8987922-B2
Application number	US-201313802306-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 11, 2013
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first bond pad above the substrate;
a passivation layer over the substrate, the passivation layer having a first portion above the bond pad;
a guard ring above the substrate; and
a first alignment mark in and/or above a second portion of the passivation layer, the first alignment mark being between the first bond pad and the guard ring.

2. The semiconductor device of claim 1 , wherein the first alignment mark is of a shape selected from a group comprising essentially of a circle, a square, a diamond, an L shape, or a hollow shape.

3. The semiconductor device of claim 1 , wherein the first alignment mark is at a same layer above the substrate as the first bond pad.

4. The semiconductor device of claim 1 , further comprising:
a passivation layer on the substrate, covering a first part of the first bond pad while exposing a second part of the first bond pad;
a first polymer layer on the passivation layer and partially exposing the first bond pad;
a post-passivation interconnect (PPI) layer above the first polymer layer and in contact with the first bond pad; and
wherein the first alignment mark is at the PPI layer above the first polymer layer.

5. The semiconductor device of claim 4 , further comprising a second alignment mark at a different layer from the PPI layer.

6. The semiconductor device of claim 4 , further comprising:
a connector on the PPI layer, wherein the connector is between the first bond pad and the guard ring, and the first alignment mark is between the connector and the guard ring.

7. The semiconductor device of claim 4 , further comprising:
a second polymer layer on the first polymer layer, and on the PPI layer with an opening to expose the PPI layer;
an under-bump metallurgy (UBM) layer over the second polymer layer, covering the opening of the second polymer layer and electrically connected to the PPI layer; and
a connector on the UBM layer, wherein the connector is between the first bond pad and the guard ring, and the first alignment mark is between the connector and the guard ring.

8. The semiconductor device of claim 1 , further comprising:
a second bond pad above the substrate, wherein the first bond pad and the second bond pad are within an area surrounded by the guard ring; and
a second alignment mark on the substrate, between the second bond pad and the guard ring.

9. The semiconductor device of claim 1 , wherein the first alignment mark is at a corner of an area surrounded by the guard ring, and the first bond pad is within the area.

10. The semiconductor device of claim 1 , wherein the first alignment mark is close to an edge of an area surrounded by the guard ring, and the first bond pad is within the area.

11. A semiconductor device, comprising:
a substrate;
a first bond pad above the substrate;
a guard ring above the substrate;
a passivation layer on the substrate, covering a part of the first bond pad while exposing the first bond pad;
a first polymer layer on the passivation layer and partially exposing the first bond pad;
a post-passivation interconnect (PPI) layer above the first polymer layer and in contact with the first bond pad; and
a first alignment mark above the substrate, between the first bond pad and the guard ring.

12. The semiconductor device of claim 11 , wherein the first alignment mark is at the PPI layer above the first polymer layer.

13. The semiconductor device of claim 11 , further comprising a second alignment mark at a different layer from a layer the first alignment mark is at.

14. The semiconductor device of claim 11 , further comprising:
a connector on the PPI layer, wherein the connector is between the first bond pad and the guard ring, the first alignment mark is between the connector and the guard ring.

15. The semiconductor device of claim 11 , further comprising:
a second polymer layer on the first polymer layer, and on the PPI layer with an opening to expose the PPI layer;
an under-bump metallurgy (UBM) layer over the second polymer layer, covering the opening of the second polymer layer and electrically connected to the PPI layer; and
a connector on the UBM layer, wherein the connector is between the first bond pad and the guard ring, the first alignment mark is between the connector and the guard ring.

16. A semiconductor device comprising:
a bond pad on a substrate;
a passivation layer over the substrate and the bond pad, a first opening being defined through the passivation layer to the bond pad;
a guard ring along an edge of the passivation layer;
a first alignment mark in and/or above the passivation layer, the first alignment mark being between the bond pad and the guard ring;
an interconnection over the passivation layer, the interconnection being coupled to the bond pad through the first opening; and
an external connector being coupled to the interconnection.

17. The semiconductor device of claim 16 , wherein the first alignment mark is in the passivation layer.

18. The semiconductor device of claim 16 further comprising:
a polymer layer over the passivation layer, a second opening being defined through the polymer layer and the first opening to the bond pad, the interconnection being over the polymer layer and coupled to the bond pad through the second opening.

19. The semiconductor device of claim 18 , wherein the first alignment mark is over the polymer layer.

20. The semiconductor device of claim 19 further comprising a second alignment mark in the passivation layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Tsung-Yuan
• Chen Hsien-Wei
• Lu Wen-Hsiung
• Lin Hung-Jen

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title