Semiconductor package

Patent metadata

Field	Value
Publication number	US-12021020-B2
Application number	US-202117149216-A
Country	US
Kind code	B2
Filing date	Jan 14, 2021
Priority date	Jul 10, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed in the first insulating layer;
a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer;
a vertical connection structure disposed on the first surface of the first redistribution structure and electrically connected to the first redistribution layer;
an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure;
a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and
a connection bump disposed on the second surface of the first redistribution structure and electrically connected to the first redistribution layer,
wherein the vertical connection structure includes a pattern layer embedded in the first insulating layer, a barrier layer disposed on the pattern layer, and a pillar layer disposed on the barrier layer,
wherein the semiconductor chip has a bottom surface on which the connection pad is disposed,
wherein the first insulating layer contacts a lower surface and a side surface of the connection pad, a lower surface and a side surface of the pattern layer, and the bottom surface of the semiconductor chip,
wherein the pattern layer overlaps the barrier layer in a vertical direction and the connection pad in a horizontal direction perpendicular to the vertical direction, and
wherein an uppermost width of the barrier layer in the horizontal direction is equal to or less than a lowermost width of the pillar layer in the horizontal direction.

2. The semiconductor package of claim 1 ,
wherein a thickness of the pillar layer is greater than a thickness of the pattern layer and a thickness of the barrier layer, and
wherein the thickness of the pattern layer is greater than the thickness of the barrier layer.

3. The semiconductor package of claim 2 ,
wherein the thickness of the pillar layer is within a range of 100 μm to 200 μm,
wherein the thickness of the barrier layer is within a range of 1 μm to 2 μm, and
wherein the thickness of the pattern layer is within a range of 5 μm to 10 μm.

4. The semiconductor package of claim 1 , wherein the barrier layer includes a material different from materials of the pillar layer and the pattern layer.

5. The semiconductor package of claim 4 ,
wherein the barrier layer includes nickel (Ni) or titanium (Ti), and
wherein the pillar layer and the pattern layer include copper (Cu).

6. The semiconductor package of claim 1 , wherein at least a portion of an upper surface of the pattern layer is exposed from the first insulating layer.

7. The semiconductor package of claim 1 , wherein the encapsulant covers at least a portion of each of a side surface of the pillar layer, a side surface of the barrier layer, and an upper surface of the pattern layer.

8. The semiconductor package of claim 1 , wherein a lower surface of the encapsulant is coplanar with a lower surface of the barrier layer.

9. The semiconductor package of claim 1 , wherein the pillar layer has a vertical cross-sectional shape of which a side surface is tapered, such that a width of the pillar layer increases towards the barrier layer.

10. The semiconductor package of claim 1 , further comprising:
a core structure disposed adjacent to the vertical connection structure on the first surface of the first redistribution structure,
wherein the core structure includes a first core layer embedded in the first insulating layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer,
wherein a thickness of the first core layer is the same as a thickness of the pattern layer,
wherein a thickness of the second core layer is the same as a thickness of the barrier layer, and
wherein a thickness of the third core layer is the same as a thickness of the pillar layer.

11. The semiconductor package of claim 10 , wherein the core structure is electrically insulated from the vertical connection structure.

12. The semiconductor package of claim 1 ,
wherein the second redistribution structure further includes a second insulating layer disposed on the encapsulant, and a second redistribution via penetrating the second insulating layer and electrically connecting the second redistribution layer to the vertical connection structure, and
wherein the second redistribution layer is disposed on an upper surface of the second insulating layer.

13. A semiconductor package, comprising:
a redistribution structure including an insulating layer and a redistribution layer disposed on the insulating layer;
a semiconductor chip disposed on the redistribution structure and including a connection pad electrically connected to the redistribution layer, the connection pad embedded in a first surface of the insulating layer, opposite to a second surface of the insulating layer on which the redistribution layer is disposed; and
a vertical connection structure surrounding the semiconductor chip and electrically connected to the redistribution layer on the redistribution structure,
wherein the vertical connection structure includes a pattern layer comprising segments embedded in the first surface, a barrier layer disposed on the pattern layer, and a pillar layer disposed on the barrier layer,
wherein the segments have a first pad portion in contact with a lower surface of the barrier layer and overlapping the pillar layer in a vertical direction, a second pad portion spaced apart from the first pad portion, and a pattern portion extending from the first pad portion to the second pad portion in a horizontal direction,
wherein a thickness of the barrier layer in the vertical direction is less than a thickness of the pattern layer in the vertical direction,
wherein a length of the barrier layer in the horizontal direction is less than a total length of at least one of the segments of the pattern layer in the horizontal direction,
wherein a bottom surface of the semiconductor chip contacts with the first surface of the insulating layer,
wherein the connection pad and the pattern layer are at a level below the first surface of the insulating layer in the vertical direction,
wherein the barrier layer is at a level above the first surface of the insulating layer in the vertical direction, and
wherein the pattern layer overlaps the connection pad in the horizontal direction.

14. The semiconductor package of claim 13 ,
wherein the pattern portion has a lane shape that connects the first pad portion to the second pad portion, and
wherein at least a portion of the pattern portion is in contact with the lower surface of the barrier layer.

15. The semiconductor package of claim 13 , wherein the first pad portion has a shape extending from one end of the pattern portion with a same line width as a line width of the pattern portion.

16. The semiconductor package of claim 13 ,
wherein the semiconductor chip has an active surface on which the connection pad is disposed, and further includes a first protective layer disposed on the active surface and covering the connection pad, a second protective layer disposed on the first protective layer, and a connection post penetrating the first pr

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Kim Jeongseok
• Cho Bongju

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title