Semiconductor module

Patent metadata

Field	Value
Publication number	US-10607940-B2
Application number	US-201816057655-A
Country	US
Kind code	B2
Filing date	Aug 7, 2018
Priority date	Aug 8, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.

First claim

What is claimed is:

1. A semiconductor module, comprising:
a metal core layer that includes:
a first metal layer; and
a second metal layer on the first metal layer,
wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer;

a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component; and
a first insulating layer covering the second metal layer and the semiconductor element in the cavity;
a first conductive pattern provided on the first insulating layer, the first conductive pattern being electrically connected to the semiconductor element;
a second insulating layer covering a rear surface of the first metal layer; and
a second conductive pattern provided on a rear surface of the second insulating layer, the second conductive pattern being electrically connected to the semiconductor element.

2. The semiconductor module according to claim 1 , wherein, in the metal core layer, the second metal layer is thinner than the first metal layer.

3. The semiconductor module according to claim 1 , wherein the first metal layer is formed of a metal material that is harder than a metal material of the second metal layer.

4. The semiconductor module according to any one of claim 1 , wherein the second metal layer is patterned to have a prescribed shaped section in a plan view that is electrically connected to at least one of the semiconductor element and the first conductive pattern.

5. The semiconductor module according to claim 1 , wherein the second metal layer is patterned to have a first shaped metal section and a second shaped metal section that are physically separated and isolated from the first shaped metal section in a plan view, the first shaped metal section being electrically connected to at least one of the semiconductor element and the first conductive pattern.

6. The semiconductor module according to claim 5 , wherein the exposed surface of the first metal layer that forms the bottom surface of the cavity is connected to the semiconductor element such that heat of the semiconductor element is transferred.

7. The semiconductor module according to claim 1 , wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the first metal layer than in the second metal layer.

8. The semiconductor module according to claim 2 , wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the first metal layer than in the second metal layer.

9. The semiconductor module according to claim 3 , a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the first metal layer than in the second metal layer.

10. The semiconductor module according to claim 1 ,
wherein the metal core layer further includes an interlayer insulating layer interposed between the first metal layer and the second metal layer, and a portion of the interlayer insulating layer that is underneath said portion of the second metal layer is removed to define said cavity, exposing said surface of the first metal layer as the bottom surface of the cavity, and
wherein the bottom surface of the cavity has the smoother surface profile than the surface of the first metal layer that is not exposed by the cavity and under the second metal layer.

11. A semiconductor module, comprising:
a metal core layer that includes:
a first metal layer;
a second metal layer on the first metal layer; and
a third metal layer on the second metal layer,
wherein a portion of the third metal layer and a portion of the second metal layer that is underneath said portion of the third metal layer are removed to expose a surface of the first metal layer, the removed portion of the second and third metal layers defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer;

a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component; and
a first insulating layer covering the third metal layer and the semiconductor element in the cavity;
a first conductive pattern provided on the first insulating layer, the first conductive pattern being electrically connected to the semiconductor element;
a second insulating layer covering a rear surface of the first metal layer; and
a second conductive pattern provided on a rear surface of the second insulating layer, the second conductive pattern being electrically connected to the semiconductor element.

12. The semiconductor module according to claim 11 , wherein, in the metal core layer, the second metal layer is thinner than the first metal layer, and the third metal layer is thinner than the second metal layer.

13. The semiconductor module according to claim 11 ,
wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the first metal layer than in the second metal layer and in the third metal layer.

Assignees

• Taiyo Yuden Kk

Inventors

• Sugiyama Yuichi
• Miyazaki Masashi
• Hamada Yoshiki

Classifications

• H05K3/4608

  comprising an electrically conductive base or core · CPC title

• H05K1/0207

  using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes · CPC title

• H05K1/0263

  High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board (H05K1/0293 takes precedence) · CPC title

• H05K1/0271

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title