Package structure with porous conductive structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11482491-B2
Application number	US-201815877398-A
Country	US
Kind code	B2
Filing date	Jan 23, 2018
Priority date	Nov 8, 2017
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

First claim

What is claimed is:

1. A package structure, comprising:
an insulating encapsulation;
at least one die, encapsulated in the insulating encapsulation, wherein a sidewall of the at least one die is in contact with the insulating encapsulation;
conductive structures, located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures being electrically connected to the at least one die;
conductive terminals, disposed on a rear side of the at least one die, electrically coupled to the at least one die, and free from the insulating encapsulation, wherein positioning locations of the conductive terminals are within a positioning location of the at least one die, and the conductive terminals are laterally surrounded by the conductive structures in a vertical projection in a stacking direction of the conductive terminals and the at least one die; and
a first redistribution layer, disposed on the at least one die, wherein the conductive structures are in direct contact with a first metallization layer of the first redistribution layer,
wherein each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof,
wherein each of the conductive structures has a plurality of pores distributed therein.

2. The package structure of claim 1 , wherein the first surface of the each of the conductive structures is a planar surface, and the first surface of the each of the conductive structures is levelled with and coplanar to an active surface of the at least one die.

3. The package structure of claim 1 , wherein the conductive structures penetrate and are electrically connected to the first redistribution layer, and the first surface of the each of the conductive structures is a curved surface and protrudes out of the first redistribution layer.

4. The package structure of claim 1 ,
wherein the first redistribution layer is disposed between the at least one die and the conductive terminals in the stacking direction and in contact with the insulating encapsulation, wherein the conductive terminals are electrically coupled to the at least one die through the first redistribution layer and the conductive structures.

5. The package structure of claim 1 , further comprising:
a second redistribution layer, disposed over the insulating encapsulation and electrically connected to the at least one die, wherein the insulating encapsulation is disposed between the first redistribution layer and the second redistribution layer, wherein the conductive structures are electrically connected to the at least one die through the second redistribution layer.

6. The package structure of claim 5 , wherein the conductive structures further extends into the second redistribution layer and in direct contact with a second metallization layer of the second redistribution layer.

7. The package structure of claim 1 , wherein a thickness of the conductive structures is greater than a thickness of the at least one die in the stacking direction.

8. A package structure, comprising:
a first redistribution layer and a second redistribution layer;
a semiconductor die, located between and electrically connected to the first redistribution layer and the second redistribution layer;
a conductive structure, located between and electrically connected to the first redistribution layer and the second redistribution layer, and located aside of and electrically connected to the semiconductor die, wherein the conductive structure has a first surface with a top diameter, a second surface with a bottom diameter opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and the top diameter is greater than the bottom diameter, wherein the conductive structure has a plurality of pores distributed therein, wherein the conductive structure is in direct contact with a first metallization layer of the first redistribution layer;
an insulating encapsulation, encapsulating the semiconductor die and surrounding the conductive structure, wherein a sidewall of the semiconductor die is in contact with the insulating encapsulation; and
conductive terminals, disposed on a rear side of the semiconductor die, electrically coupled to the semiconductor die, and free from the insulating encapsulation, wherein positioning locations of the conductive terminals are within a positioning location of the semiconductor die, and the conductive terminals are laterally surrounded by the conductive structure in a vertical projection in a stacking direction of the conductive terminals and the semiconductor die.

9. The package structure of claim 8 , wherein the first surface is located between the first redistribution layer and the second redistribution layer along a stacking direction of the first redistribution layer, the semiconductor die and the second redistribution layer.

10. The package structure of claim 8 , wherein the first redistribution layer is located between the first surface and the second redistribution layer along a stacking direction of the first redistribution layer, the semiconductor die and the second redistribution layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Chen Chih-Hua
• Hsieh Ching-Hua
• Lin Hsiu-Jen
• Huang Yu-Chih
• Tsai Yu-Peng
• Cheng Chia-Shen
• Tsao Chih-Chiang
• Yu Jen-Jui

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title