Subtractive patterning of interconnect structures

Patent metadata

Field	Value
Publication number	US-12020949-B2
Application number	US-202117447388-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 10, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

First claim

What is claimed is:

1. A method of making a back-end-of-line (BEOL) component, comprising:
filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material;
forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material;
removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material;
recessing the layer of metal material where the top surface of the layer of metal material is exposed; and
removing the scaffolding material.

2. The method of claim 1 , further comprising:
depositing the layer of metal material onto a substrate;
depositing the layer of hardmask material onto the layer of metal material; and
patterning the layer of metal material and the layer of hardmask material to form the spaces.

3. The method of claim 1 , wherein forming the at least one plug includes:
removing a portion of the layer of hardmask material to expose a portion of the layer of metal material; and
covering the exposed portion of the layer of metal material with the at least one plug.

4. The method of claim 3 , wherein covering the exposed portion of the layer of metal material includes forming the at least one plug in direct contact with the layer of metal material.

5. The method of claim 1 , further comprising:
encapsulating the layer of metal material in an ultra-low-k dielectric material.

6. The method of claim 1 , further comprising:
forming at least one further plug on top of the layer of metal material such that the at least one further plug is integrally formed with the layer of scaffolding material, wherein:
removing the layer of hardmask material includes removing the layer of hardmask material such that the top surface of the layer of metal material is exposed except where the at least one plug and the at least one further plug are formed on top of the layer of metal material.

7. The method of claim 6 , wherein forming the at least one further plug includes:
removing a further portion of the layer of hardmask material to expose a further portion of the layer of metal material; and
covering the exposed further portion of the layer of metal material with the at least one further plug.

8. A computerized system for making a back-end-of-line (BEOL) component, comprising:
a memory; and
a processor communicatively coupled to the memory, wherein the processor is configured to perform a method comprising:
filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material;
forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material;
removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material;
recessing the layer of metal material where the top surface of the layer of metal material is exposed; and
removing the scaffolding material.

9. The system of claim 8 , wherein the method further comprises:
depositing the layer of metal material onto a substrate;
depositing a layer of hardmask material onto the layer of metal material; and
patterning the layer of metal material and the layer of hardmask material to form the spaces.

10. The system of claim 8 , wherein forming the at least one plug includes:
removing a portion of the layer of hardmask material to expose a portion of the layer of metal material; and
covering the exposed portion of the layer of metal material with the at least one plug.

11. The system of claim 10 , wherein covering the exposed portion of the layer of metal material includes forming the at least one plug in direct contact with the layer of metal material.

12. The system of claim 8 , wherein the method further comprises encapsulating the layer of metal material in an ultra-low-k dielectric material.

13. The system of claim 8 , wherein:
the method further comprises forming at least one further plug on top of the layer of metal material such that the at least one further plug is integrally formed with the layer of scaffolding material, and
removing the layer of hardmask material includes removing the layer of hardmask material such that the top surface of the layer of metal material is exposed except where the at least one plug and the at least one further plug are formed on top of the layer of metal material.

14. The system of claim 13 , wherein forming the at least one further plug includes:
removing a further portion of the layer of hardmask material to expose a further portion of the layer of metal material; and
covering the exposed further portion of the layer of metal material with the at least one further plug.

15. A method for making a back-end-of-line (BEOL) component, the method comprising:
depositing a metal layer on a substrate;
patterning the metal layer to form one or more conductive elements;
forming a scaffolding structure including a plug arranged on top of a portion of the patterned metal layer;
selectively recessing the metal layer such that the portion of the patterned metal layer covered by the plug is not recessed; and
removing the scaffolding structure.

16. The method of claim 15 , wherein patterning the metal layer includes depositing a layer of hardmask material onto the metal layer and patterning the layer of hardmask material.

17. The method of claim 16 , wherein forming the scaffolding structure including the plug includes:
removing a portion of the patterned layer of hardmask material to expose a portion of the patterned metal layer; and
covering the exposed portion of the patterned metal layer with the plug.

18. The method of claim 17 , wherein covering the exposed portion of the patterned metal layer includes forming the plug in direct contact with the patterned metal layer.

19. The method of claim 16 , further comprising:
forming a further plug arranged on top of a further portion of the patterned metal layer such that the further plug is integrally formed with the scaffolding structure, and
selectively recessing the metal layer such that the further portion of the patterned metal layer covered by the further plug is not recessed.

20. The method of claim 19 , wherein forming the further plug includes:
removing a further portion of the patterned layer of hardmask material to expose a further portion of the patterned metal layer; and
covering the exposed further portion of the patterned metal layer with the further plug.

Assignees

• IBM

Inventors

• Metzler Dominik
• Ghosh Somnath
• Arnold John Christopher
• De Silva Ekmini Anuja

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/063 Primary

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title