Self-aligned interconnects formed using substractive techniques

Patent metadata

Field	Value
Publication number	US-9761489-B2
Application number	US-201313987667-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Aug 20, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

First claim

We claim:

1. A method of forming an interconnect conductive contact structure useful for Nodes of N10 or lower, wherein said contact structure has an effective resistivity of 20 μohm-cm or less and said Electron Mean Free Path is 20 nm or lower, and wherein a plurality of subtractive processes are used to fabricate structures comprising conductive contact pillars or other conductive contact shapes which are self aligned relative to underlying conductive line contacts, to provide conductive contact pillars which are solid, and without a presence of voids, wherein a starting structure from which said interconnect conductive contact structures are formed comprises a horizontal base layer which is a conductive layer; a line metal conductive layer overlying said base layer; an etch stop layer overlying said line metal layer; a pillar-forming conductive layer overlying said etch stop layer; a second etch stop layer overlying said pillar-forming conductive layer; a hard masking layer overlying said second etch stop layer; and a lithographic patterning structure overlying said second etch stop layer; and wherein conductive contact pillars and conductive line contacts are formed upon etching of said starting structure using said plurality of subtractive processes.

2. An interconnect conductive contact structure formed using the method of claim 1 , wherein said contact structure may be used overlying an upper surface of a semiconductor device or overlying an upper surface of a MEMS structural device, wherein said semiconductor device or said MEMS structural device is compatible with a 10 nm Node down to a 5 nm Node, or lower.

Assignees

• Applied Materials Inc

Inventors

• Mebarki Bencherki
• Dai Huixiong
• Chen Yongmei
• Ren He
• Naik Mehul

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title