Via formation using sidewall image transfer process to define lateral dimension

Patent metadata

Field	Value
Publication number	US-10157789-B2
Application number	US-201615239178-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	May 13, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a via including:
an elongated conductive body extending through a dielectric layer to a conductive wire in an underlying layer, wherein the elongated conductive body splits into at least two prongs above the underlying layer; and
a first pillar and a second pillar on the underlying layer and above the conductive wire abutting each of the at least two prongs of-the elongated conductive body at a position nearest the underlying layer to define a lateral dimension of the elongated conductive body.

2. The semiconductor device of claim 1 , wherein each first pillar is spaced from each second pillar and having a lower portion of the elongated conductive body there between, each pillar defining the lateral dimension of the elongated conductive body.

3. The semiconductor device of claim 2 , further comprising a third pillar spaced from one of the first and second pillars, and wherein each pillar includes a spacer material and a layer of the spacer material extending between the third pillar and the one of the first and second pillars.

4. The semiconductor device of claim 3 , further comprising an organic planarizing layer (OPL) over the layer of the spacer material.

5. The semiconductor device of claim 1 , wherein the pillar has a lateral thickness between 5 nanometers and 15 nanometers.

6. The semiconductor device of claim 1 , wherein the pillar has a sub-lithographic lateral dimension.

7. A via structure for a semiconductor device, the via structure comprising:
an elongated conductive body extending through a dielectric layer to a conductive wire in an underlying layer, wherein the elongated conductive body splits into a prong above the underlying layer; and
a first pillar and a second on the underlying layer and above the conductive wire abutting each of the at least two prongs of the elongated conductive body at a position nearest the underlying layer to define a lateral dimension of the elongated body.

8. The via structure of claim 7 , further comprising a third pillar spaced from one of the first or second pillars, and wherein each pillar includes a spacer material and the third pillar and a layer of the spacer material extending between the third pillar and the one of the first or second pillars.

9. The via structure of claim 8 , further comprising an organic planarizing layer (OPL) over the layer of the spacer material.

10. The via structure of claim 7 , wherein each pillar has a lateral thickness between 5 nanometers and 15 nanometers.

11. The via structure of claim 7 , wherein each pillar has a sub-lithographic dimension.

Assignees

• IBM
• Globalfoundries Inc
• St Microelectronics Inc

Inventors

• Chen Shyng-Tsong
• Chi Cheng
• Liu Chi-Chun
• Mignot Sylvie M
• Mignot Yann A
• Shobha Hosadurga K
• Spooner Terry A
• Wang Wenhui
• Xu Yongan

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title