Subtractive etch interconnects

US10177031B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10177031-B2
Application numberUS-201414580259-A
CountryUS
Kind codeB2
Filing dateDec 23, 2014
Priority dateDec 23, 2014
Publication dateJan 8, 2019
Grant dateJan 8, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming a first trench in a first inter-layer dielectric (ILD) and a first cap, wherein the first cap is on a substrate and the first ILD is on the first cap, wherein the first trench exposes a lower metal line, and wherein the lower metal line is in the substrate; forming a first barrier layer on the first ILD and in the first trench; forming an integrated metal layer on the first barrier layer, wherein the integrated metal layer includes a first metal line and a first via, wherein the first metal line is above the first ILD and the first via is in the first trench, wherein the first metal line is in direct contact with the first via, and wherein a top surface of the integrated metal layer is planar; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line, wherein the isolation trench is not directly above the first via, and wherein the isolation trench extends at least partially into the first ILD; forming a second barrier layer in the isolation trench, such that the second barrier layer extends at least partially into the first ILD; removing a portion of the second barrier layer from a bottom of the isolation trench to expose the first ILD; forming a second ILD on the second barrier and in the isolation trench, wherein a bottom surface of the second ILD is on the first ILD, and the bottom surface of the second ILD being below a top surface of the first ILD and below the first metal line; and removing the second ILD and the second barrier layer from above the integrated metal layer, wherein the first hardmask is formed between a top portion of the second barrier layer and the integrated metal layer, and the first hardmask is a diffusion barrier. 2. The method of claim 1 , wherein a portion of the second ILD in the isolation trench extends 10 to 50 percent into the first ILD. 3. The method of claim 1 , further comprising: removing the first barrier layer from a bottom surface of the isolation trench using a sputtering process; and removing a portion of the first ILD at the bottom of the isolation trench. 4. The method of claim 1 , wherein the second barrier layer is a metallic material. 5. The method of claim 1 , further comprising: forming a second cap on the second ILD and above the first metal layer; forming a second trench in the second cap, wherein a portion the integrated metal layer is exposed; and forming a second integrated metal layer on the second cap and in the second trench, wherein the second integrated metal layer includes a second metal line and a second via, wherein the second metal line is above the second ILD and the second via is in the second trench, and wherein a top surface of the second integrated metal layer is planar. 6. A method comprising: forming a first trench in a first dielectric layer, wherein the first dielectric layer is on a substrate, wherein the first trench exposes a lower metal line, and wherein the lower metal line is in the substrate; forming a first barrier layer on the first dielectric layer and in the first trench; forming an integrated metal layer on the first barrier layer, wherein the integrated metal layer includes a first metal line and a first via, wherein the first metal line is above the first dielectric layer and the first via is in the first trench, and wherein a top surface of the integrated metal layer is planar; forming a patterned first hardmask on the integrated metal layer; forming an isolation trench in the first metal line using the patterned first hardmask as a mask, wherein the patterned first hardmask defines a boundary of the isolation trench, wherein the isolation trench is not directly above the first via, and wherein the isolation trench extends at least partially into the first dielectric layer; forming a second barrier layer in the isolation trench, such that the second barrier layer extends at least partially into the first dielectric layer; removing a portion of the second barrier layer from a bottom of the isolation trench to expose the first dielectric layer; forming an inter-layer dielectric (ILD) on the second barrier and in the isolation trench, wherein a bottom surface of the ILD is below a top surface of the first dielectric layer; and removing the ILD and the second barrier layer from above the integrated metal layer, wherein the first hardmask is formed between a top portion of the second barrier layer and the integrated metal layer, and the first hardmask is a diffusion barrier. 7. The method of claim 6 , wherein a portion of the ILD in the isolation trench extends 10 to 50 percent into the first dielectric layer. 8. The method of claim 6 , further comprising: removing the first barrier layer from a bottom surface of the isolation trench using a sputtering process; and removing a portion of the first dielectric layer at the bottom of the isolation trench. 9. The method of claim 6 , wherein the first via is in direct contact with the first metal line. 10. The method of claim 6 , further comprising: forming a cap on the ILD and above the first metal layer; forming a second trench in the cap, wherein a portion the integrated metal layer is exposed; and forming a second integrated metal layer on the cap and in the second trench, wherein the second integrated metal layer includes a second metal line and a second via, wherein the second metal line is above the ILD and the second via is in the second trench, and wherein a top surface of the second integrated metal layer is planar.

Assignees

Inventors

Classifications

  • using subtractive patterning of the conductive members · CPC title

  • using masks for insulating materials · CPC title

  • using masks for conductive or resistive materials · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • by forming conductive members before forming protective insulating material · CPC title

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What does patent US10177031B2 cover?
A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; fo…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W20/47. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 08 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).