Interconnect structure having subtractive etch feature and damascene feature

US9601426B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9601426-B1
Application numberUS-201615166570-A
CountryUS
Kind codeB1
Filing dateMay 27, 2016
Priority dateJan 28, 2016
Publication dateMar 21, 2017
Grant dateMar 21, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

First claim

Opening claim text (preview).

What is claimed is: 1. An interconnect structure comprising: a first insulator layer; a first dielectric layer on the first insulator layer; a subtractive etch feature comprising a first conductive material, the subtractive etch feature having a first subtractive etch vertical wall, a second subtractive etch vertical wall, and an angle between the first subtractive etch vertical wall and a horizontal plane that is less than 90 degrees; and a damascene feature comprising a second conductive material, the damascene feature having a first damascene vertical wall, a second damascene vertical wall, and an angle between the first damascene vertical wall and the horizontal plane that is greater than 90 degrees; wherein the first subtractive etch vertical wall is parallel to the second damascene vertical wall. 2. The interconnect structure according to claim 1 , further comprising a via having a first via upper wall, wherein the first via upper wall is parallel to the first subtractive etch vertical wall or to the first damascene vertical wall. 3. The interconnect structure according to claim 1 , wherein the first conductive material comprises a first conductive material selected from the group consisting of tungsten, copper, gold, silver, cobalt, aluminum, and alloys thereof. 4. The interconnect structure according to claim 1 , further comprising a second insulator layer. 5. The interconnect structure according to claim 1 , wherein the second conductive material is selected from the group consisting of tungsten, copper, gold, silver, cobalt, aluminum, and alloys thereof.

Assignees

Inventors

Classifications

  • using subtractive patterning of the conductive members · CPC title

  • Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • of conductive or resistive materials · CPC title

  • by chemical means · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9601426B1 cover?
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive ma…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W20/435. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).