High density interconnection and wiring layers, package structures, and integration methods

Patent metadata

Field	Value
Publication number	US-12015003-B2
Application number	US-202117488968-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Sep 29, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

First claim

What is claimed is:

1. An interconnect for a semiconductor device, the interconnect comprising:
a laminate substrate;
a first plurality of electrical devices in or on a surface of the laminate substrate;
a redistribution layer having a surface disposed on the surface of the laminate substrate using a handle layer;
a second plurality of electrical devices in or on the surface of the redistribution layer; and
a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices;
wherein the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other such that the first plurality of electrical devices and the second plurality of electrical devices are interconnected upon removal of the handle layer to form a dielectric structure and a conductor structure.

2. The interconnect of claim 1 , wherein the transmission lines comprise metal posts extending from the first plurality of electrical devices.

3. The interconnect of claim 1 , wherein the transmission lines comprises vias extending from the first plurality of electrical devices.

4. The interconnect of claim 1 , further comprising an adhesive dielectric layer between the redistribution layer and the laminate substrate.

5. The interconnect of claim 1 , wherein the first plurality of electrical devices and the second plurality of electrical devices are connected using a solder interconnect.

6. The interconnect of claim 1 , wherein the surface of the laminate substrate and the surface of the redistribution layer are adhesively joined.

7. A method of forming a semiconductor device, the method comprising:
forming a coreless laminate substrate;
forming a first plurality of electrical devices in or on a surface of the laminate substrate;
forming interconnection ports at the first plurality of electrical devices;
forming a redistribution layer on a handle layer, the redistribution layer having a second plurality of electrical devices on or in a surface of the redistribution layer;
connecting the redistribution layer to the laminate substrate using the handle layer such that the second plurality of electrical devices is interconnected to the first plurality of electrical devices through the interconnection ports;
wherein when the redistribution layer is connected to the laminate substrate, the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other.

8. The method of claim 7 , wherein the coreless laminate substrate is formed by sequential deposition of layers to form a board.

9. The method of claim 7 , wherein forming interconnection ports at the first plurality of electrical devices comprises forming metal posts at the first plurality of electrical devices.

10. The method of claim 7 , wherein forming interconnection ports at the first plurality of electrical devices comprises forming vias at the first plurality of electrical devices.

11. The method of claim 7 , wherein connecting the redistribution layer to the laminate substrate comprises applying flowable adhesive dielectric material between the redistribution layer and the laminate substrate.

12. The method of claim 7 , further comprising applying an adhesive between the surface of the laminate substrate and the surface of the redistribution layer.

13. A method for fabricating an interconnect for a semiconductor device, the method comprising:
forming a multi-layer base substrate;
forming a first plurality of electrical and/or optical semiconductor devices in or on a surface of the multi-layer base substrate;
forming first ends of interconnection ports at the first plurality of electrical and/or optical semiconductor devices;
forming a second plurality of electrical and/or optical semiconductor devices at second ends of the interconnection ports distal from the first ends;
forming a redistribution layer on a handle layer, the redistribution layer having a third plurality of electrical and/or optical semiconductor devices in or on the redistribution layer;
connecting the redistribution layer to the handle layer;
disposing the handle layer onto the second plurality of electrical and/or optical semiconductor devices; and
removing the handle layer;
wherein the surface of the multi-layer base substrate and the surface of the redistribution layer are parallel to each other to form dielectric and conductor structures.

14. The method of claim 13 , wherein the multi-layer base substrate is formed by sequential deposition of layers to form a board.

15. The method of claim 13 , wherein the multi-layer base substrate is famed from one or more dielectric materials selected from glass and organic polymers and from one or more electrical conductors and/or optical conductors selected from copper, nickel, gold, tungsten, titanium, tantalum, solder, silicon, and silicon nitride.

16. The method of claim 13 , wherein the multi-layer base substrate comprises electrical and/or optical interconnections.

17. The method of claim 13 , wherein the interconnection ports are metal posts or vias.

18. The method of claim 13 , further comprising disposing a lid on the redistribution layer opposite to the handle layer.

19. The method of claim 13 , wherein the surface of the multi-layer base substrate and the surface of the redistribution layer are adhesively joined.

Assignees

• IBM

Inventors

• Knickerbocker John
• Farooq Mukta Ghate
• Sakuma Katsuyuki

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W76/167

  the container walls comprising an aperture, e.g. for pressure control · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title