Semiconductor package

Patent metadata

Field	Value
Publication number	US-9520373-B2
Application number	US-201514978550-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Apr 13, 2015
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on the one surface of the semiconductor chip. The redistribution structure includes a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer. The redistribution insulating layer includes a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant. The first insulating portion and the second insulating portion are connected to each other in a horizontal direction.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip having one surface on which chip pads are formed; and
a redistribution structure formed on the one surface of the semiconductor chip,
wherein the redistribution structure comprises a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer,
the redistribution insulating layer comprises a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant, and
the first insulating portion and the second insulating portion are connected to each other in a horizontal direction.

2. The semiconductor package 1 , wherein the chip pads comprise a power pad, a ground pad, and a signal pad,
wherein a first region of the semiconductor chip, in which the power pad and the ground pad are disposed, overlaps the first insulating portion, and
wherein a second region of the second chip, in which the signal pad is disposed, overlaps the second insulating portion.

3. The semiconductor package of claim 1 , wherein the power pad is configured to be connected to a power source disposed outside the semiconductor package, and the ground pad is configured to be connected to a ground disposed outside the semiconductor package, and
the signal pad is configured to receive and transmit signals from and to the outside of the semiconductor package.

4. The semiconductor package of claim 2 , wherein the first dielectric constant is higher than the second dielectric constant.

5. The semiconductor package of claim 1 , wherein the second dielectric constant ranges from 1.5 to 6.9, and
the first dielectric constant ranges from 7 to 1000.

6. The semiconductor package of claim 1 , wherein the first insulating portion and the second insulating portion have coplanar surfaces on which the redistribution layer is disposed.

7. The semiconductor package of claim 1 , wherein the first insulating portion is disposed in a region that overlaps a central region of the semiconductor chip in a plan view.

8. The semiconductor package of claim 7 , wherein the second insulating portion is disposed in a region that surrounds the first insulating portion in the plan view.

9. The semiconductor package of claim 1 , further comprising:
external connection terminals connected to the redistribution layer; and
an outermost insulating layer formed to cover at least portions of the redistribution layer and the external connection terminals, the outermost insulating layer having a third dielectric constant.

10. The semiconductor package of claim 9 , wherein the third dielectric constant is lower than the first dielectric constant.

11. A semiconductor package comprising:
a semiconductor chip comprising a first region in which a power pad and a ground pad are disposed and a second region in which a signal pad is disposed; and
a redistribution structure disposed on the first and second regions of the semiconductor chip,
wherein the redistribution structure comprises:
at least one redistribution layer connected to the chip pads; and
at least one redistribution insulating layer disposed between the at least one redistribution layer and the semiconductor chip,

wherein the at least one redistribution insulating layer comprises a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is lower than the first dielectric constant, and
the first insulating portion overlaps the first region of the semiconductor chip, and the second insulating portion overlaps the second region of the semiconductor chip.

12. The semiconductor package of claim 11 , wherein the at least one redistribution layer comprises a plurality of redistribution layers spaced apart from one another in a vertical direction,
wherein the power pad is connected to a first redistribution layer selected out of the redistribution layers, and the ground pad is connected to a second redistribution layer that is different from the first redistribution layer selected out of the redistribution layers.

13. The semiconductor package of claim 11 , wherein the at least one redistribution insulating layer comprises first and second redistribution insulating layers,
wherein the first redistribution insulating layer comprises the first insulating portion having the first dielectric constant and the second insulating portion having the second dielectric constant, and
the second redistribution insulating layer comprises a third insulating portion that overlaps the first insulating portion and has a third dielectric constant, and a fourth insulating portion that overlaps the second insulating portion and has a fourth dielectric constant that is lower than the third dielectric constant.

14. The semiconductor package 11 , wherein the at least one redistribution insulating layer comprises first and second redistribution insulating layers,
wherein the first redistribution insulating layer comprises the first insulating portion having the first dielectric constant and the second insulating portion having the second dielectric constant, and
the second redistribution insulating layer has a third dielectric constant that is lower than the first dielectric constant.

15. The semiconductor package 11 , further comprising a mold unit disposed on the redistribution structure to cover the semiconductor chip.

16. A semiconductor package comprising:
a printed circuit board (PCB); and
a semiconductor chip mounted on the PCB,
wherein the PCB comprises:
a body resin having a top surface and a bottom surface; and
an interconnection pattern formed on at least one of the top surface and the bottom surface of the body resin,

wherein the body resin comprises a first body portion having a first dielectric constant and a second body portion having a second dielectric constant that is different from the first dielectric constant.

17. The semiconductor package of claim 16 , wherein the first dielectric constant of the first body portion is higher than the second dielectric constant of the second body portion.

18. The semiconductor package of claim 16 , wherein the first dielectric constant ranges from 7 to 1000.

19. The semiconductor package of claim 16 , wherein the semiconductor chip comprises a power pad, a ground pad, and a signal pad,
wherein the first body portion is disposed in a region that overlaps the power pad and the ground pad, and
the second body portion is disposed in a region that overlaps the signal pad.

20. The semiconductor package of claim 16 , wherein the first body portion is disposed in a region that overlaps a central region of the semiconductor chip in a plan view, and
the second body portion is disposed in a region that surrounds the first body portion in the plan view.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yong-Hoon
• Kim Keung-Beum

Classifications

• H10W72/874

  On different surfaces · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/655

  Fan-out layouts · CPC title