Multi-chip structure and method of forming same

Patent metadata

Field	Value
Publication number	US-9324698-B2
Application number	US-201414177947-A
Country	US
Kind code	B2
Filing date	Feb 11, 2014
Priority date	Aug 13, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer. The device further comprises a redistribution layer formed on a top surface of a first side of the encapsulation layer, wherein the redistribution layer is connected to active circuits of the first chip and the second chip and the redistribution layer extends beyond at least one edge of the first chip and the second chip.

First claim

What is claimed is:

1. A device comprising:
a fan-out structure comprising:
a redistribution layer disposed on a first side of the fan-out structure;
a dielectric layer disposed over the redistribution layer; and
a plurality of first bumps disposed over the dielectric layer and on a second side of the fan-out structure;

a first chip disposed over the first side of the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer;
a second chip disposed over the first chip, wherein:
the second chip is connected to the first chip through a plurality of second bumps; and

a molding compound layer disposed over the first side of the fan-out structure, wherein the first chip and the second chip are embedded in the molding compound layer, and wherein at least one edge of the first chip is not vertically aligned with a corresponding edge of the second chip.

2. The device of claim 1 , wherein:
a top surface of the second chip is exposed outside the molding compound layer.

3. The device of claim 1 , wherein:
the second chip comprises a plurality of semiconductor dies stacked together.

4. The device of claim 1 , wherein:
active circuits of the second chip are electrically connected to the first bumps.

5. The device of claim 1 , further comprising:
a shift between a first centerline of the first chip and a second centerline of the second chip.

6. The device of claim 1 , wherein:
the first bumps comprise solder, copper and any combination thereof.

7. The device of claim 5 , wherein:
the shift is configured such that:
an edge of the first chip is aligned with a first edge of the fan-out structure; and
an edge of the second chip is aligned with a second edge of the fan-out structure, and wherein the first edge and the second edge are on opposite sides of the fan-out structure.

8. A device comprising:
a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer, and wherein at least one edge of the first chip is not vertically aligned with a corresponding edge of the second chip, and wherein at least one sidewall of the first chip and the second chip is exposed outside the encapsulation layer;
a redistribution layer disposed on a top surface of a first side of the encapsulation layer, wherein:
the redistribution layer is connected to active circuits of the first chip and the second chip; and
the redistribution layer extends beyond at least one edge of the first chip and the second chip; and

a plurality of conductive bumps disposed over the redistribution layer and connected to the redistribution layer.

9. The device of claim 8 , further comprising:
a dielectric layer disposed between the plurality of conductive bumps and the top surface of the first side of the encapsulation layer.

10. The device of claim 8 , further comprising:
a plurality of bumps disposed between the first chip and the second chip.

11. The device of claim 8 , wherein:
a top surface of the multi-chip structure is exposed outside a second side of the encapsulation layer.

12. The device of claim 8 , wherein:
the second chip comprises a plurality of semiconductor dies stacked together.

13. The device of claim 8 , wherein:
the first chip and the second chip are configured such that:
the first chip is shifted to a first edge of the encapsulation layer; and
the second chip is shift to a second edge of the encapsulation layer, wherein the first edge and the second edge are on opposite sides of the encapsulation layer.

14. The device of claim 13 , wherein:
an edge of the first chip is aligned with the first edge of the encapsulation layer; and
an edge of the second chip is aligned with the second edge of the encapsulation layer.

15. A method comprising:
attaching a plurality of stacked semiconductor dies on a carrier through an adhesive layer;
mounting a semiconductor chip on a top surface of the plurality of stacked semiconductor dies;
forming a molding compound layer over the carrier, wherein the plurality of stacked semiconductor dies and the semiconductor chip are embedded in the molding compound layer, and wherein at least one edge of the stacked semiconductor dies is not vertically aligned with a corresponding edge of the semiconductor chip;
grinding the molding compound layer until a surface of the semiconductor chip is exposed;
forming a redistribution layer on the surface of the semiconductor chip; and
forming a plurality of conductive bumps over the redistribution layer.

16. The method of claim 15 , further comprising:
forming the redistribution layer on the surface of the semiconductor chip, wherein:
the redistribution layer extends beyond one edge of the semiconductor chip; and
the redistribution layer extends beyond one edge of the plurality of stacked semiconductor dies.

17. The method of claim 15 , further comprising:
attaching the semiconductor chip on the plurality of stacked semiconductor dies; and
applying a reflow process so that the semiconductor chip is bonded on the top surface of the plurality of stacked semiconductor dies to form a multi-chip structure.

18. The method of claim 15 , further comprising:
depositing a dielectric layer on the redistribution layer.

19. The method of claim 15 , wherein:
the stacked semiconductor dies are memory circuits; and
the semiconductor chip includes a logic circuit.

20. The method of claim 18 , further comprising:
forming a plurality of under bump metallization (UBM) structures in the dielectric layer; and
forming the plurality of conductive bumps over the UBM structures.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang

Classifications

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title