Package substrate

Patent metadata

Field	Value
Publication number	US-10373918-B2
Application number	US-201715440461-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Jul 25, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art.

First claim

The invention claimed is:

1. A package substrate, comprising:
a redistribution structure having a plurality of top electrode pads, the plurality of top electrode pads being configured with a first density adaptive for a chip to mount thereon;
a build-up layer configured on bottom of the redistribution structure, the build-up layer having a plurality of bottom mounting pads, the plurality of bottom mounting pads being configured with a second density adaptive for the substrate to mount onto a printed circuit board, the second density being lower than the first density;
a molding layer embedding the redistribution structure therein; a groove extending around the redistribution structure; and
a dielectric material filled in the groove,
wherein
the groove contains no conductive material,
an open end surface of the groove is at the same height as a top surface of the redistribution structure,
the top surface of the redistribution structure is a surface of the redistribution structure farthest away to the build-up layer,
a depth of the groove is greater than an entire thickness of the redistribution structure,
a first portion of the molding layer is interposed between the groove and the redistribution structure,
the material of the dielectric material filled in the groove is different from the material of the molding layer, and
a second portion of the molding layer is interposed, in a thickness direction of the package substrate, between the redistribution structure and the build-up layer.

2. A package substrate as claimed in claim 1 , wherein a width of the first portion of the molding layer is smaller than a width of the groove.

3. A package substrate as claimed in claim 1 , further comprising:
a chip mounted on the plurality of top electrode pads,
wherein
the redistribution structure and the groove are entirely below the chip,
the build-up layer includes a topmost dielectric layer in which a topmost circuitry of the build-up layer is embedded,
the groove extends from a top surface of the molding layer, through an entire thickness of the molding layer, and into the topmost dielectric layer of the build-up layer, and
the molding layer has a bottom surface in direct contact with a top surface of the topmost dielectric layer of the build-up layer.

4. A package substrate as claimed in claim 1 , wherein the dielectric material filled in the groove is silicone.

5. A package substrate as claimed in claim 1 , further comprising: an interposer embedded in the redistribution structure.

6. A package substrate as claimed in claim 5 , wherein the dielectric material filled in the groove is silicone.

7. A package substrate, comprising:
a redistribution structure having a plurality of top electrode pads, the plurality of top electrode pads being configured with a first density;
a build-up layer configured on bottom of the redistribution structure, the build-up layer having a plurality of bottom mounting pads, the plurality of bottom mounting pads being configured with a second density adaptive for the substrate to mount onto a printed circuit board, the second density being lower than the first density;
a molding layer embedding the redistribution structure therein; and
a groove extending around the redistribution structure,
wherein
an open end surface of the groove is at the same height as a top surface of the redistribution structure,
the top surface of the redistribution structure is a surface of the redistribution structure farthest away from the build-up layer,
a depth of the groove is greater than an entire thickness of the redistribution structure,
the groove contains no conductive material, and
the groove extends from a top surface of the molding layer, through an entire thickness of the molding layer, and into a portion of the build-up layer.

8. A package substrate as claimed in claim 7 , wherein a bottom of the groove is below a bottommost circuitry of the redistribution structure.

9. A package substrate as claimed in claim 7 , wherein a portion of the groove above the bottom of the groove is embedded in the build-up layer with a topmost circuitry.

10. A package substrate as claimed in claim 9 , wherein
the build-up layer includes a topmost dielectric layer in which the topmost circuitry of the build-up layer is embedded, and
the molding layer has a bottom surface in direct contact with a top surface of the topmost dielectric layer of the build-up layer.

11. A package substrate as claimed in claim 7 , further comprising:
an interposer embedded in the redistribution structure.

12. A package substrate as claimed in claim 7 , wherein
the build-up layer includes a topmost dielectric layer in which a topmost circuitry of the build-up layer is embedded, and
the molding layer has a bottom surface in direct contact with a top surface of the topmost dielectric layer of the build-up layer.

13. A package substrate as claimed in claim 12 , wherein the groove extends continuously around the redistribution structure.

14. A package substrate as claimed in claim 12 , wherein the groove abuts the redistribution structure.

15. A package substrate as claimed in claim 12 , wherein, in a top plan view, the groove comprises four independent section grooves arranged along four sides of the redistribution structure, respectively.

16. A package substrate as claimed in claim 12 , wherein, in a top plan view, the groove comprises a plurality of holes arranged along four sides of the redistribution structure.

17. A package substrate as claimed in claim 12 , wherein, in a top plan view, the groove comprises a plurality of rectangular grooves arranged along four sides of the redistribution structure.

18. A package substrate as claimed in claim 12 , further comprising: an interposer embedded in the redistribution structure.

Assignees

• Hu Dyi Chung

Inventors

• Hu Dyi-Chung

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title