SRAM bit cells with three-dimensional integration

Patent metadata

Field	Value
Publication number	US-12009326-B2
Application number	US-202217584507-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Jan 26, 2022
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

First claim

What is claimed is:

1. A structure for a static random access memory bitcell, the structure comprising:
a first substrate;
a second substrate;
a first n-type field-effect transistor on the first substrate, the first n-type field-effect transistor including a first gate;
a second n-type field-effect transistor on the first substrate, the second n-type field-effect transistor including a second gate;
a first p-type field-effect transistor on the second substrate, the first p-type field-effect transistor including a first gate and a first source/drain region;
a second p-type field-effect transistor on the second substrate, the second p-type field-effect transistor including a second gate and a second source/drain region;
a first interconnect structure on the first substrate, the first interconnect structure including a first metal feature and a second metal feature, the first metal feature of the first interconnect structure connected to the first gate of the first n-type field-effect transistor, the second metal feature of the first interconnect structure connected to the second gate of the second n-type field-effect transistor, the first metal feature including a first surface, and the second metal feature including a second surface; and
a second interconnect structure on the second substrate, the second interconnect structure including a first metal feature and a second metal feature, the first metal feature of the second interconnect structure connected to the first gate of the first p-type field-effect transistor, the second metal feature of the second interconnect structure connected to the second gate of the second p-type field-effect transistor, the first metal feature of the second interconnect structure including a first surface that is connected to the first surface of the first metal feature of the first interconnect structure, and the second metal feature of the second interconnect structure including a second surface that is connected to the second surface of the second metal feature of the first interconnect structure,
wherein the first metal feature of the second interconnect structure is further connected to the first source/drain region of the first p-type field-effect transistor, and the second metal feature of the second interconnect structure is further connected to the second source/drain region of the second p-type field-effect transistor.

2. The structure of claim 1 wherein the first interconnect structure includes a third metal feature, and further comprising:
an inter-tier via extending through the first substrate to the third metal feature.

3. The structure of claim 2 wherein the first metal feature and the third metal feature are positioned in different metallization levels of the first interconnect structure.

4. The structure of claim 1 wherein the second interconnect structure includes a third metal feature, and further comprising:
an inter-tier via extending through the first substrate and the first interconnect structure to the third metal feature.

5. The structure of claim 4 wherein the second metal feature and the third metal feature are positioned in different metallization levels of the second interconnect structure.

6. The structure of claim 1 wherein the first interconnect structure includes a third metal feature and a fourth metal feature, and further comprising:
a bit line connected to the third metal feature; and
a ground line connected to the fourth metal feature,
wherein the first metal feature and the second metal feature are laterally offset from the bit line.

7. The structure of claim 6 wherein the ground line is aligned transverse to the bit line.

8. The structure of claim 7 further comprising:
a word line aligned transverse to the ground line.

9. The structure of claim 1 wherein the second interconnect structure includes a third metal feature, and further comprising:
a supply voltage line connected to the third metal feature,
wherein the supply voltage line is laterally offset relative to the third metal feature.

10. The structure of claim 1 wherein the first surface of the first metal feature of the second interconnect structure connected to the first surface of the first metal feature of the first interconnect structure by a first metal-to-metal bond, and the second surface of the second metal feature of the second interconnect structure is connected to the second surface of the second metal feature of the first interconnect structure by a second metal-to-metal bond.

11. The structure of claim 1 wherein the first substrate includes a first active region and a second active region, and further comprising:
a well in the first active region of the first substrate and in the second active region of the first surface substrate, wherein the first n-type field-effect transistor includes a first source/drain region in the first active region, the second n-type field-effect transistor includes a second source/drain region disposed in the second active region, and the first n-type field-effect transistor and the second n-type field-effect transistor share the well.

12. The structure of claim 11 further comprising:
a third n-type field-effect transistor on the first substrate, the third n-type field-effect transistor including a third gate and a third source/drain region; and
a fourth n-type field-effect transistor on the first substrate, the fourth n-type field-effect transistor including a fourth gate and a fourth source/drain region,
wherein the third source/drain region is disposed in the first active region, the fourth source/drain region is disposed in the second active region, and the third n-type field-effect transistor and the fourth n-type field-effect transistor share the well with the first n-type field-effect transistor and the second n-type field-effect transistor.

13. The structure of claim 1 wherein the first n-type field-effect transistor and the second n-type field-effect transistor are pull-down transistors of the static random access memory bitcell, and the first p-type field-effect transistor and the second p-type field-effect transistor are pull-up transistors of the static random access memory bitcell.

14. A method of forming a structure for a static random access memory bitcell, the method comprising:
forming a first n-type field-effect transistor on a first substrate, wherein the first n-type field-effect transistor includes a first gate;
forming a second n-type field-effect transistor on the first substrate, wherein the second n-type field-effect transistor includes a second gate;
forming a first p-type field-effect transistor on a second substrate, wherein the first p-type field-effect transistor includes a first gate;
forming a second p-type field-effect transistor on the second substrate, wherein the second p-type field-effect transistor includes a second gate and a second source/drain region;
forming a first interconnect structure on the first substrate, wherein the first interconnect structure includes a first metal feature and a second metal feature, the first metal feature of the first interconnect structure is connected to the first gate of the first n-type field-effect transistor, the second metal feature of the first interconnect structure is connected to the second gate of the second n-type field-effect transistor, the first metal feature includes a first surface, and the second metal feature includes a second surface;
forming a second interconnect structure on the second substrate, wherein the second interconnect structure includes a first metal feature and a second metal feature, the first metal feature of the second inter

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Balan Hari
• Tan Juan Boon
• Chockalingam Ramasamy
• Yi Wanbing

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title