Three-dimensional memory device with static random-access memory

Patent metadata

Field	Value
Publication number	US-10811071-B1
Application number	US-201916455656-A
Country	US
Kind code	B1
Filing date	Jun 27, 2019
Priority date	May 17, 2019
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Embodiments of three-dimensional (3D) memory devices with a 3D memory device includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit, an array of static random-access memory (SRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and
a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

2. The 3D memory device of claim 1 , wherein the first semiconductor structure comprises:
a substrate;
the peripheral circuit on the substrate;
the array of SRAM cells on the substrate and non-overlapping with the peripheral circuit; and
the first bonding layer above the peripheral circuit and the array of SRAM cells.

3. The 3D memory device of claim 2 , wherein the second semiconductor structure comprises:
the second bonding layer above the first bonding layer;
a memory stack above the second bonding layer;
the array of 3D NAND memory strings extending vertically through the memory stack; and
a semiconductor layer above and in contact with the array of 3D NAND memory strings.

4. The 3D memory device of claim 3 , further comprising a pad-out interconnect layer above the semiconductor layer.

5. The 3D memory device of claim 3 , wherein the semiconductor layer comprises at least one of polysilicon or single-crystal silicon.

6. The 3D memory device of claim 1 , wherein the second semiconductor structure comprises:
a substrate;
a memory stack above the substrate;
the array of 3D NAND memory strings extending vertically through the memory stack; and
the second bonding layer above the memory stack and the array of 3D NAND memory strings.

7. The 3D memory device of claim 6 , wherein the first semiconductor structure comprises:
the first bonding layer above the second bonding layer;
the peripheral circuit above the first bonding layer;
the array of SRAM cells above the first bonding layer and non-overlapping with the peripheral circuit; and
a semiconductor layer above and in contact with the peripheral circuit and the array of SRAM cells.

8. The 3D memory device of claim 7 , further comprising a pad-out interconnect layer above the semiconductor layer.

9. The 3D memory device of claim 1 , wherein the peripheral circuit and the array of SRAM cells are stacked one over another.

10. The 3D memory device of claim 1 , wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the array of SRAM cells, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of 3D NAND memory strings.

11. The 3D memory device of claim 1 , wherein the 3D memory device is packaged in at least one of an embedded multi-media card (eMMC) or a universal flash storage (UFS).

12. The 3D memory device of claim 1 , wherein each SRAM cell comprises a plurality of transistors.

13. The 3D memory device of claim 10 , wherein the array of SRAM cells are electrically connected to the array of 3D NAND memory strings through the first and second interconnect layers and the first and second bonding contacts.

14. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first semiconductor structure comprising a peripheral circuit, an array of static random-access memory (SRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts;
forming a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and
bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

15. The method of claim 14 , wherein forming the first semiconductor structure comprises:
forming the peripheral circuit and the array of SRAM cells on a first substrate;
forming a first interconnect layer above the peripheral circuit and the array of SRAM cells; and
forming the first bonding layer above the first interconnect layer.

16. The method of claim 15 , wherein forming the peripheral circuit and the array of SRAM cells comprises forming a plurality of transistors on the first substrate.

17. The method of claim 14 , wherein forming the second semiconductor structure comprises:
forming a memory stack above a second substrate;
forming the array of 3D NAND memory strings extending vertically through the memory stack;
forming a second interconnect layer above the array of 3D NAND memory strings; and
forming the second bonding layer above the second interconnect layer.

18. The method of claim 14 , further comprising:
thinning the second substrate to form a semiconductor layer after the bonding; and
forming a pad-out interconnect layer above the semiconductor layer.

19. The method of claim 14 , wherein the first semiconductor structure is above the second semiconductor structure after the bonding.

20. The method of claim 19 , further comprising:
thinning the first substrate to form a semiconductor layer after the bonding; and
forming a pad-out interconnect layer above the semiconductor layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li yue ping
• Hou Chun Yuan

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title