Stacked three-dimensional heterogeneous memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11056454-B2
Application number	US-201916727889-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Apr 15, 2019
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

Embodiments of three-dimensional (3D) memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes NAND memory cells and a first bonding layer including first bonding contacts. The 3D memory device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The 3D memory device also includes a third semiconductor structure including SRAM cells, a third bonding layer including third bonding contacts, and a fourth bonding layer including fourth bonding contacts. The third and fourth bonding layers are on both sides of the SRAM cells. The semiconductor device further includes a first bonding interface between the first and third bonding layers. The first bonding contacts are in contact with the third bonding contacts at the first bonding interface. The 3D memory device further includes a second bonding interface between the second and fourth bonding layers. The second bonding contacts are in contact with the fourth bonding contacts at the second bonding interface.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
a third semiconductor structure comprising an array of static random-access memory (SRAM) cells, a third bonding layer comprising a plurality of third bonding contacts, and a fourth bonding layer comprising a plurality of fourth bonding contacts, wherein the third bonding layer and the fourth bonding layer are on both sides of the array of SRAM cells;
a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with the third bonding contacts at the first bonding interface; and
a second bonding interface between the second bonding layer and the fourth bonding layer, the second bonding contacts being in contact with the fourth bonding contacts at the second bonding interface.

2. The 3D memory device of claim 1 , wherein the second semiconductor structure comprises:
a substrate;
the array of DRAM cells above the substrate; and
the second bonding layer above the array of DRAM cells.

3. The 3D memory device of claim 2 , wherein the third semiconductor structure comprises:
the fourth bonding layer above the second bonding layer;
the array of SRAM cells above the fourth bonding layer; and
the third bonding layer above the array of SRAM cells.

4. The 3D memory device of claim 3 , wherein the first semiconductor structure comprises:
the first bonding layer above the third bonding layer;
the array of NAND memory cells above the first bonding layer; and
a semiconductor layer above and in contact with the array of NAND memory cells.

5. The 3D memory device of claim 4 , further comprising a pad-out interconnect layer above the semiconductor layer.

6. The 3D memory device of claim 1 , wherein the first semiconductor structure comprises:
a substrate;
the array of NAND memory cells above the substrate; and
the first bonding layer above the array of NAND memory cells.

7. The 3D memory device of claim 6 , wherein the third semiconductor structure comprises:
the third bonding layer above the first bonding layer;
the array of SRAM cells above the third bonding layer; and
the fourth bonding layer above the array of SRAM cells.

8. The 3D memory device of claim 7 , wherein the second semiconductor structure comprises:
the second bonding layer above the fourth bonding layer;
the array of DRAM cells above the second bonding layer; and
a semiconductor layer above and in contact with the array of DRAM cells.

9. The 3D memory device of claim 8 , further comprising a pad-out interconnect layer above the semiconductor layer.

10. The 3D memory device of claim 1 , wherein
the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the array of NAND memory cells;
the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells;
the array of SRAM cells is electrically connected to the array of NAND memory cells through the first interconnect layer and the first and third bonding contacts; and
the array of SRAM cells is electrically connected to the array of DRAM cells through the second interconnect layer and the second and fourth bonding contacts.

11. The 3D memory device of claim 10 , wherein the array of NAND memory cells is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first, second, third, and fourth bonding contacts.

12. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of static random-access memory (SRAM) cells and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
a third semiconductor structure comprising an array of NAND memory cells, a third bonding layer comprising a plurality of third bonding contacts, and a fourth bonding layer comprising a plurality of fourth bonding contacts, wherein the third bonding layer and the fourth bonding layer are on both sides of the array of NAND memory cells;
a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with the third bonding contacts at the first bonding interface; and
a second bonding interface between the second bonding layer and the fourth bonding layer, the second bonding contacts being in contact with the fourth bonding contacts at the second bonding interface.

13. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
forming a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
forming a third semiconductor structure comprising an array of static random-access memory (SRAM) cells and a third bonding layer comprising a plurality of third bonding contacts;
bonding the third semiconductor structure and one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the first and second bonding layers;
forming a fourth bonding layer comprising a plurality of fourth bonding contacts in the third semiconductor structure, wherein the third bonding layer and the fourth bonding layer are on both sides of the array of SRAM cells; and
bonding the bonded structure and another one of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another one of the first and second bonding layers.

14. The method of claim 13 , wherein forming the first semiconductor structure comprises:
forming the array of NAND memory cells above a first substrate;
forming a first interconnect layer above the array of NAND memory cells; and
forming the first bonding layer above the first interconnect layer.

15. The method of claim 13 , wherein forming the second semiconductor structure comprises:
forming the array of DRAM cells above a second substrate;
forming a second interconnect layer above the array of DRAM cells; and
forming the second bonding layer above the second interconnect layer.

16. The method of claim 13 , wherein forming the third semiconductor structure comprises:
forming the array of SRAM cells on a third substrate;
forming a third interconnect layer above the array of SRAM cells; and
forming the third bonding layer above the third interconnect layer.

17. The method of 16 , further comprising:
thinning the third substrate after bonding the third semiconductor structure and one of the first and second semiconductor structures;
forming a contact extending vertically through the thinned third substrate to be in contact with the third interconnect layer; and
forming the fourth bonding layer on the thinned third substrate an

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Liu Jun

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title