Quadrature circuit interconnect architecture with clock forwarding

Patent metadata

Field	Value
Publication number	US-11979480-B2
Application number	US-202217933557-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	Sep 20, 2022
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

First claim

What is claimed is:

1. An integrated circuit communication architecture comprising:
a clock lane configured to send a clock signal at a first rate from a first chip to a second chip;
a clock divider on the second chip, the clock divider configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal, the first divided clock signal and the second divided clock signal being sent at reduced rates compared to the first rate, the clock divider maintaining current mode logic properties for the first and second divided clock signals; and
multiple receivers on the second chip, each of the multiple receivers comprising its own de-skew circuit configured to receive and process the first divided clock signal and the second divided clock signal from the clock divider to allow for sampling of data transmitted from the first chip to the second chip.

2. The integrated circuit communication architecture of claim 1 , wherein the first rate is a half rate compared to a data rate.

3. The integrated circuit communication architecture of claim 1 , wherein the first divided clock signal is an in-phase clock signal and runs at one quarter of a data rate.

4. The integrated circuit communication architecture of claim 1 , wherein the second divided clock signal is a quadrature clock signal and runs at one quarter of a data rate.

5. The integrated circuit communication architecture of claim 1 , wherein the clock divider comprises one or more current mode logic circuits for low clock jitter.

6. The integrated circuit communication architecture of claim 1 , wherein a first de-skew circuit comprises one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

7. The integrated circuit communication architecture of claim 1 , wherein the reduced rate of the first divided clock signal is half of the first rate.

8. The integrated circuit communication architecture of claim 1 , wherein the reduced rate of the second divided clock signal is half of the first rate.

9. The integrated circuit communication architecture of claim 1 , further comprising a driver on the first chip for driving the clock signal across the clock lane.

10. The integrated circuit communication architecture of claim 1 , further comprising a data lane configured to transmit data from the first chip to the second chip.

11. The integrated circuit communication architecture of claim 1 , wherein a first de-skew circuit is disposed in a first receiver of the multiple receivers of the second chip, and the clock divider serves the multiple receivers on the second chip.

12. A method of integrated circuit communication, the method comprising:
transmitting a clock signal via a clock lane and at a first rate from a first chip to a second chip;
dividing the transmitted clock signal via a clock divider at the second chip to form a first divided clock signal and a second divided clock signal having reduced rates compared to the first rate;
maintaining, via the clock divider, current mode logic properties for the first and second divided clock signals; and
inputting the first divided clock signal and the second divided clock signal into multiple receivers of the first chip, wherein each of the multiple receivers comprises its own de-skew circuit and the inputting into the multiple receivers occurs into the de-skew circuits.

13. The method of claim 12 , wherein the first rate is a half rate.

14. The method of claim 12 , wherein the first divided clock signal is an in-phase clock signal and runs at one quarter of a data rate.

15. The method of claim 12 , wherein the second divided clock signal is a quadrature clock signal and runs at one quarter of a data rate.

16. The method of claim 12 , wherein the clock divider comprises one or more current mode logic circuits for low clock jitter.

17. The method of claim 12 , wherein a first de-skew circuit comprises one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

18. An integrated circuit communication architecture comprising:
a clock lane configured to send a clock signal at a first rate from a first chip to a second chip;
a clock divider on the second chip, the clock divider configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal, the first divided clock signal and the second divided clock signal being sent at reduced rates compared to the first rate; and
first and second receivers on the second chip, the first receiver including a first de-skew circuit, the second receiver including a second de-skew circuit, wherein the first and second de-skew circuits are configured to receive and process the first divided clock signal and the second divided clock signal from the clock divider to allow for sampling of data transmitted from the first chip to the second chip;
wherein the clock divider is configured to serve both the first receiver and the second receiver with each of the first divided clock signal and the second divided clock signal.

19. The integrated circuit communication architecture of claim 18 , wherein the first divided clock signal is an in-phase clock signal and runs at one quarter of a data rate.

20. The integrated circuit communication architecture of claim 18 , wherein the second divided clock signal is a quadrature clock signal and runs at one quarter of a data rate.

Assignees

• IBM

Inventors

• Sperling Michael
• Dreps Daniel Mark
• English Erik
• Qi Jieming

Classifications

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L7/0012 Primary

  by comparing receiver clock with transmitter clock · CPC title

• H04L25/247

  for synchronous signals · CPC title