Clock-forwarding memory controller with mesochronously-clocked signaling interface

Patent metadata

Field	Value
Publication number	US-10901485-B2
Application number	US-201916418259-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	Jan 12, 2009
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

First claim

What is claimed is:

1. A memory controller component comprising:
a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;
a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;
a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;
a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and
clocking circuitry to generate at least the second, third and fourth clock signals, the clocking circuitry including:
phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and
circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and
clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re-start transmission of the first clock signal to the DRAM at conclusion of the first interval.

2. The memory controller component of claim 1 wherein the first, third and fourth clock signals oscillate at a first frequency and wherein the circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals comprises circuitry to generate the second clock signal at half the first frequency.

3. The memory controller component of claim 1 wherein the write-data transmitter to transmit the write data to the DRAM in response to the third clock signal comprises circuitry to transmit a first portion of the write data at a time corresponding to a rising edge of the third clock signal and a second portion of the write data at a time corresponding to a falling edge of the third clock signal.

4. The memory controller component of claim 1 wherein the clocking circuitry further includes circuitry to generate the first clock signal and the clock transmitter receives the first clock signal from the clock-generator circuitry and outputs the first clock signal to the DRAM via a clock signaling link.

5. The memory controller component of claim 4 wherein the clock-generator circuitry comprises a phase-locked-loop (PLL) that receives a reference clock signal and generates, as the first clock signal, a frequency-multiplied version of the reference clock signal.

6. The memory controller component of claim 1 wherein:
the write-data transmitter to transmit the write data to the DRAM in response to a third clock signal comprises circuitry to transmit the write data in a sequence of continuous bit intervals defined by the third clock signal; and
the clocking circuitry further includes circuitry to generate the first clock signal at a first frequency in which the first clock signal transitions at least once per constituent bit interval of the sequence of continuous bit intervals.

7. The memory controller component of claim 6 wherein:
the phase control circuitry is coupled to receive the first clock signal and includes phase-adjust circuitry to generate, as the third clock signal, a phase-shifted version of the first clock signal that oscillates at the first frequency; and
the circuitry to transmit the write data in the sequence of continuous bit intervals defined by the third clock signal comprises circuitry to transmit the write data on a data signaling link at both rising and falling edges of the third clock signal to achieve a data transmission rate twice the first frequency.

8. The memory controller component of claim 7 wherein the clocking circuitry to generate the third clock signal comprises circuitry to generate, as the third clock signal, a differential clock signal constituted by complementary component clock signals and wherein the circuitry to transmit the write data on the data signaling link at both rising and falling edges of the third clock signal comprises circuitry to transmit a first portion of the write data in response to a rising edge of one of the complementary component clock signals and to transmit a second portion of the write data in response to a rising edge of the other of the complementary component clock signals.

9. The memory controller component of claim 1 wherein the phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal comprises first phase control circuitry to offset the phase of the third clock signal relative to the first clock signal such that the write data transmitted by the write-data transmitter in response to the third clock signal arrives at the write-data receive circuitry of the DRAM in a desired phase relation with the first clock signal.

10. The memory controller component of claim 9 wherein the phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal further comprises second phase control circuitry to offset the phase of the fourth clock signal relative to the first clock signal such that the fourth clock signal is aligned, within the read-data receiver, with the read data transmitted by the DRAM.

11. The memory controller component of claim 1 wherein the phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal comprises calibration circuitry to adjust the phase of the third clock signal in a calibration operation that includes transmitting test data to the DRAM via the write-data transmitter and reading back the test data from the DRAM via the read-data receiver.

12. The memory controller component of claim 1 wherein the clock-pause circuitry to halt transmission of the first clock signal to the DRAM during the first interval to conserve power comprises circuitry to halt transmission of the first clock signal to reduce power dissipation with the DRAM during the first interval.

13. The memory controller component of claim 1 further comprising circuitry to disable operation of one or more of the command/address transmitter, write-data transmitter, or read-data receiver during the first interval to further conserve power.

14. A method of operation within a memory controller component, the method comprising:
transmitting a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;
transmitting the read commands and the write commands to the DRAM in response to a second clock signal;
transmitting the write data to the DRAM in response to a third clock signal;
sampling the read data transmitted by the DRAM in response to a fourth clock signal;
independently offsetting phases of the third and fourth clock signals relative to the first clock signal;
generating the second clock signal at a lower frequency than the third and fourth clock signals;
halting transmission of the first clock signal to the DRAM during a first interval to conserve power; and
re-starting transmission of t

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W
• Fuller Andrew M

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1066

  Output synchronization · CPC title