Multi-phase clock generation circuit with digital calibration
US-12500581-B2 · Dec 16, 2025 · US
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Dreps Daniel Mark patents
Dreps Daniel Mark is listed as an inventor on 35 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Dreps Daniel Mark |
| Total patents | 35 |
| First publication | Jul 9, 2015 |
| Latest publication | Dec 16, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Clock synchronization in a multichip module
US-2025334999-A1 · Oct 30, 2025 · US
Two-stage processor voltage regulation
US-2025328177-A1 · Oct 23, 2025 · US
Dense via pitch interconnect to increase wiring density
US-12266598-B2 · Apr 1, 2025 · US
Multi-phase clock generation circuit with digital calibration
US-2025007498-A1 · Jan 2, 2025 · US
Active Inductor Peaking Buffer with Output Common Mode Control
US-2025007477-A1 · Jan 2, 2025 · US
Communication systems for power supply noise reduction
US-12176960-B2 · Dec 24, 2024 · US
Processor package substrate with high-speed top-surface connection to cable interconnect
US-2024321802-A1 · Sep 26, 2024 · US
Communication systems for power supply noise reduction
US-12095891-B2 · Sep 17, 2024 · US
Dense via pitch interconnect to increase wiring density
US-2024234284-A9 · Jul 11, 2024 · US
Recent patents
Latest publications not already listed above.
Quadrature circuit interconnect architecture with clock forwarding
US-11979480-B2 · May 7, 2024 · US
Calibrating a quadrature receive serial interface
US-11973630-B1 · Apr 30, 2024 · US
Dense via pitch interconnect to increase wiring density
US-2024136270-A1 · Apr 25, 2024 · US
Communication systems for power supply noise reduction
US-2024121013-A1 · Apr 11, 2024 · US
Communication systems for power supply noise reduction
US-2024121072-A1 · Apr 11, 2024 · US
Quadrature circuit interconnect architecture with clock forwarding
US-2024097872-A1 · Mar 21, 2024 · US
Real-time control of via stub drilling depth asymmetry
US-2024008186-A1 · Jan 4, 2024 · US
Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output
US-11804828-B2 · Oct 31, 2023 · US
Dual duty cycle correction loop for a serializer/deserializer (serdes) transmitter output
US-2023268908-A1 · Aug 24, 2023 · US
System interconnect dynamic scaling handshake using spare bit-lane
US-9558139-B2 · Jan 31, 2017 · US
System interconnect dynamic scaling handshake using spare bit-lane
US-9552319-B2 · Jan 24, 2017 · US
System interconnect dynamic scaling by lane width and operating frequency balancing
US-9529406-B2 · Dec 27, 2016 · US
System interconnect dynamic scaling by lane width and operating frequency balancing
US-9524013-B2 · Dec 20, 2016 · US
Bus interface optimization by selecting bit-lanes having best performance margins
US-9459982-B2 · Oct 4, 2016 · US
System interconnect dynamic scaling by predicting I/O requirements
US-9324031-B2 · Apr 26, 2016 · US
System interconnect dynamic scaling by predicting I/O requirements
US-9324030-B2 · Apr 26, 2016 · US
System interconnect dynamic scaling handshake using spare bit-lane
US-2016048473-A1 · Feb 18, 2016 · US
System interconnect dynamic scaling handshake using spare bit-lane
US-2016050301-A1 · Feb 18, 2016 · US
Bus interface optimization by selecting bit-lanes having best performance margins
US-9244799-B2 · Jan 26, 2016 · US
System interconnect dynamic scaling by lane width and operating frequency balancing
US-2015301575-A1 · Oct 22, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 35 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 12 |
| G06F11/3027 | 4 |
| G06F11/2007 | 4 |
| G06F11/349 | 4 |
| G06F11/3485 | 4 |