Compact and accurate quadrature clock generation circuits

Patent metadata

Field	Value
Publication number	US-10444785-B2
Application number	US-201816109656-A
Country	US
Kind code	B2
Filing date	Aug 22, 2018
Priority date	Mar 15, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.

First claim

What is claimed is:

1. A quadrature clock generation circuit comprising:
approximate quadrature clock generator with an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal; and
a first I/Q correction circuit configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output, wherein the first I/Q correction circuit comprises:
a first resonator buffer connected to the first quadrature output and the first in-phase output, wherein the first resonator buffer is in an inverting configuration; and
a second resonator buffer connected to the first quadrature output and the first in-phase output, wherein the second resonator buffer is in a non-inverting configuration.

2. The quadrature clock generation circuit of claim 1 , wherein the first I/Q correction circuit further comprises:
a first injector buffer with an input connected to the first in-phase input and a first injector buffer output connected to the first in-phase output; and
a second injector buffer with an input connected to the first quadrature input and a second injector buffer output connected to the first quadrature output.

3. The quadrature clock generation circuit of claim 2 , wherein the approximate quadrature clock, improved quadrature clock, approximate in-phase clock, and improved in-phase clock are differential signals.

4. The quadrature clock generation circuit of claim 3 , wherein the:
the first injector buffer comprises a first transistor and a second transistor, wherein:
a gate of the first transistor is configured to receive a positive differential signal from the approximate in-phase clock;
a gate of the second transistor is configured to receive a negative differential signal from the approximate in-phase clock; and
a drain of the first transistor and a drain of the second transistor are connected to the first in-phase output;

the second injector buffer comprises a third transistor and a fourth transistor, wherein:
a gate of the third transistor is configured to receive a positive differential signal from the approximate quadrature clock;
a gate of the fourth transistor is configured to receive a negative differential signal from the approximate quadrature clock; and

a drain of the third transistor and a drain of the fourth transistor are connected to the first quadrature output;
the first resonator buffer comprises a fifth transistor and a sixth transistor, wherein:
a gate of the fifth transistor is connected to is connected to the drain of the fourth transistor;
a drain of the fifth transistor is connected to the drain of the second transistor;
a gate of the sixth transistor is connected to the drain of the third transistor; and
a drain of the sixth transistor is connected to the drain of the first transistor; and

the second resonator buffer comprises a seventh transistor and a eighth transistor, wherein:
a gate of the seventh transistor is connected to is connected to the drain of the second transistor;
a drain of the seventh transistor is connected to the drain of the third transistor;
a gate of the eighth transistor is connected to the drain of the first transistor; and
a drain of the eighth transistor is connected to the drain of the fourth transistor.

5. The quadrature clock generation circuit of claim 1 , wherein the first resonator buffer and the second resonator buffer each comprise a DC voltage gain adjustment, wherein the DC voltage gain adjustment modifies at least one of a gain at a peak frequency and a bandwidth around the peak frequency.

6. The quadrature clock generation circuit of claim 1 , wherein the approximate quadrature clock generator comprises a polyphase filter.

7. The quadrature clock generation circuit of claim 1 , further comprising a second I/Q correction circuit configured to receive the improved quadrature clock at a second quadrature input and the improved in-phase clock at a second in-phase input and output an second improved quadrature clock at a second quadrature output and a second improved in-phase clock at a second in-phase output.

8. The quadrature clock generation circuit of claim 1 , wherein the approximate quadrature clock generator comprises:
an AC coupling circuit connected to the input; and
a modified I/Q correction circuit comprising:
a first injector buffer with an input connected to the first in-phase input and a first injector buffer output connected to the first in-phase output, wherein the first in-phase input further comprises a high-pass filter;
a second injector buffer with an input connected to the first quadrature input and a second injector buffer output connected to the first quadrature output;
a first resonator buffer connected to the first quadrature output and the first in-phase output; and
a second resonator buffer connected to the first quadrature output and the first in-phase output.

9. The quadrature clock generation circuit of claim 1 , wherein the first I/Q correction circuit further comprises a bias adjustment circuit configured to receive a bias current and adjust a peak frequency of the first I/Q correction circuit.

10. The quadrature clock generation circuit of claim 1 , wherein the first I/Q correction circuit further comprises an injection strength adjustment for modifying at least one of a gain, a peak frequency, or a bandwidth.

11. A method of generating a quadrature clock comprising:
receiving a forwarded clock from a channel;
generating an approximate in-phase clock and an approximate quadrature clock using an approximate quadrature clock generator;
adjusting the approximate in-phase clock and the approximate quadrature clock using a first I/Q correction circuit to generate an improved in-phase clock and an improved quadrature clock, wherein the first I/Q correction circuit comprises:
a first resonator buffer connected to a first quadrature output and a first in-phase output, wherein the first resonator buffer is in an inverting configuration; and
a second resonator buffer connected to the first quadrature output and the first in-phase output, wherein the second resonator buffer is in a non-inverting configuration; and

outputting the improved in-phase clock and improved quadrature clock.

12. The method of generating a quadrature clock of claim 11 , wherein generating the improved in-phase and quadrature clock comprises:
adjusting a phase difference between the approximate in-phase clock and approximate quadrature clock to be closer to 90 degrees; and
amplifying the approximate in-phase clock and quadrature clock.

13. The method of generating a quadrature clock of claim 11 , further comprising:
adjusting the improved in-phase clock and the improved quadrature clock using a second I/Q correction circuit to generate a further improved in-phase clock and further improved quadrature clock; and
wherein outputting the improved in-phase clock and quadrature clock comprises outputting the further improved in-phase and further improved quadrature clock.

14. The method of generating a quadrature clock of claim 11 , wherein generating the improved in-phase and improved quadrature clock using the first I/Q correction circuit comprises:
receiving the approximate in-phase clock and the approximate quadrature clock;
shifting a phase of each of the approximate in-phase clock and the approximate quadrature clock according to a reference phase shift;
gene

Assignees

• Samsung Display Co Ltd

Inventors

• Abramzon Valentin

Classifications

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03K5/151

  with two complementary outputs · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K5/15

  Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) · CPC title

• H03H7/06

  including resistors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title