Quadrature clock correction circuit for transmitters

Patent metadata

Field	Value
Publication number	US-10680592-B2
Application number	US-201715788617-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Oct 19, 2017
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

First claim

What is claimed is:

1. A transmitter, comprising:
a multiplexer circuit configured to serialize an input signal to generate an output signal based on a four-phase clock signal;
first and second clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of the four-phase clock signal;
third and fourth clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal, wherein the first, second, third and fourth clock correction circuits are each separate circuits;
a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and
a calibration circuit configured to supply first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

2. The transmitter of claim 1 , wherein each of the first, second, third, and fourth clock correction circuits comprises:
a first inverter;
a control circuit coupled in parallel with the first inverter.

3. The transmitter of claim 2 , wherein the control circuit comprises:
first and second p-channel transistors, and first and second n-channel transistors, coupled between a supply node and a ground node, where a gate of the second p-channel transistor and a gate of the second n-channel transistor are coupled to an input of the first inverter, and a drain of the second p-channel transistor and a drain of the second n-channel transistor are coupled to an output of the first inverter;
a first digital-to-analog converter (DAC) coupled to a gate of the first p-channel transistor; and
a second DAC coupled to a gate of the first n-channel transistor.

4. The transmitter of claim 3 , wherein the calibration circuit is coupled to the first DAC and the second DAC in the control circuit in each of the first, second, third, and fourth clock correction circuits.

5. The transmitter of claim 4 , wherein the calibration circuit supplies the first and second control signals to the first DAC and the second DAC, respectively, in each of the first and second clock correction circuits, and wherein the calibration circuit supplies the third and fourth control signals to the first DAC and the second DAC, respectively, in each of the third and fourth clock correction circuits.

6. The transmitter of claim 2 , wherein each clock correction circuit of the first, second, third, and fourth correction circuits comprises:
at least one second inverter coupled to the input of the first inverter; and
at least one third inverter coupled to the output of the first inverter.

7. The transmitter of claim 1 , further comprising:
a clock generator that supplies an in-phase differential clock signal to a first clock buffer having the first and second clock correction circuits and a quadrature-phase differential clock signal to a second clock buffer having the third and fourth correction circuits.

8. The transmitter of claim 1 , wherein the calibration circuit supplies a control signal to the detector circuit, and wherein the detector circuit is configured to, in response to the control signal, detect an in-phase duty cycle error, a quadrature-phase duty cycle error, and an IQ phase error.

9. The transmitter of claim 8 , wherein the calibration circuit is configured to adjust rising edges or falling edges of the in-phase and anti-in-phase clock signals in response to the in-phase duty cycle error, adjust rising edges or falling edges of the quadrature-phase and anti-quadrature phase clock signals in response to the quadrature-phase duty cycle error, and adjust both the rising edges and the falling edges of either the in-phase and anti-in-phase clock signals, or the quadrature-phase and anti-quadrature-phase clock signals, in response to the IQ phase error.

10. A method of clock correction in a transmitter, comprising:
outputting in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal from first and second clock correction circuits;
outputting quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal from third and fourth clock correction circuits, wherein the first, second, third and fourth clock correction circuits are each separate circuits;
detecting, at a detector circuit, duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal;
providing first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

11. The method of claim 10 , wherein the step of providing comprises:
supplying the first and second control signals to a first digital-to-analog converter (DAC) and a second DAC, respectively, in each of the first and second clock correction circuits; and
supplying the third and fourth control signals to a first DAC and a second DAC, respectively, in each of the third and fourth clock correction circuits.

12. The method of claim 10 , further comprising:
supplying an in-phase differential clock signal to a first clock buffer having the first and second clock correction circuits and a quadrature-phase differential clock signal to a second clock buffer having the third and fourth clock correction circuits.

13. The method of claim 10 , wherein the step of detecting comprises determining an in-phase duty cycle error, a quadrature-phase duty cycle error, and an in-phase-to-quadrature-phase (IQ) phase error.

14. The method of claim 13 , wherein the step of providing comprises:
adjusting rising edges or falling edges of the in-phase and anti-in-phase clock signals in response to the in-phase duty cycle error;
adjusting rising edges or falling edges of the quadrature-phase and anti-quadrature phase clock signals in response to the quadrature-phase duty cycle error; and
adjusting both the rising edges and the falling edges of either the in-phase and anti-in-phase clock signals, or the quadrature-phase and anti-quadrature-phase clock signals, in response to the IQ phase error.

15. A quadrature clock correction (QCC) circuit, comprising:
first and second clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal;
third and fourth clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of a four-phase clock signal, wherein the first, second, third and fourth clock correction circuits are each separate circuits;
a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and
a calibration circuit configured to supply first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

16. The QCC circuit of claim 15 , wherein each of the first, second, third, and fourth clock correction circuits comprises:
a first inverter;
a control circuit coupled in parallel with the first inverter.

17. The QCC circuit of claim 16 , w

Assignees

• Xilinx Inc

Inventors

• Zhao Hai Bing
• Tan Kee Hian
• Chiang Ping-Chuan
• Frans Yohan

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title